#include <io.h>\r
#endif\r
#include <assert.h>\r
+#include <stdbool.h>\r
#include <stdio.h>\r
#include <stdlib.h>\r
#include <string.h>\r
UINT32 Num\r
)\r
{\r
- if (Num >= mEhdr->e_shnum)\r
- return NULL;\r
+ if (Num >= mEhdr->e_shnum) {\r
+ Error (NULL, 0, 3000, "Invalid", "GetShdrByIndex: Index %u is too high.", Num);\r
+ exit(EXIT_FAILURE);\r
+ }\r
+\r
return (Elf_Shdr*)((UINT8*)mShdrBase + Num * mEhdr->e_shentsize);\r
}\r
\r
return (Offset + mCoffAlignment - 1) & ~(mCoffAlignment - 1);\r
}\r
\r
+STATIC\r
+UINT32\r
+DebugRvaAlign (\r
+ UINT32 Offset\r
+ )\r
+{\r
+ return (Offset + 3) & ~3;\r
+}\r
+\r
//\r
// filter functions\r
//\r
return (BOOLEAN) (Shdr->sh_flags & (SHF_WRITE | SHF_ALLOC)) == (SHF_ALLOC | SHF_WRITE);\r
}\r
\r
+STATIC\r
+BOOLEAN\r
+IsStrtabShdr (\r
+ Elf_Shdr *Shdr\r
+ )\r
+{\r
+ Elf_Shdr *Namedr = GetShdrByIndex(mEhdr->e_shstrndx);\r
+\r
+ return (BOOLEAN) (strcmp((CHAR8*)mEhdr + Namedr->sh_offset + Shdr->sh_name, ELF_STRTAB_SECTION_NAME) == 0);\r
+}\r
+\r
+STATIC\r
+Elf_Shdr *\r
+FindStrtabShdr (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 i;\r
+ for (i = 0; i < mEhdr->e_shnum; i++) {\r
+ Elf_Shdr *shdr = GetShdrByIndex(i);\r
+ if (IsStrtabShdr(shdr)) {\r
+ return shdr;\r
+ }\r
+ }\r
+ return NULL;\r
+}\r
+\r
+STATIC\r
+const UINT8 *\r
+GetSymName (\r
+ Elf_Sym *Sym\r
+ )\r
+{\r
+ if (Sym->st_name == 0) {\r
+ return NULL;\r
+ }\r
+\r
+ Elf_Shdr *StrtabShdr = FindStrtabShdr();\r
+ if (StrtabShdr == NULL) {\r
+ return NULL;\r
+ }\r
+\r
+ assert(Sym->st_name < StrtabShdr->sh_size);\r
+\r
+ UINT8* StrtabContents = (UINT8*)mEhdr + StrtabShdr->sh_offset;\r
+\r
+ bool foundEnd = false;\r
+ UINT32 i;\r
+ for (i= Sym->st_name; (i < StrtabShdr->sh_size) && !foundEnd; i++) {\r
+ foundEnd = StrtabContents[i] == 0;\r
+ }\r
+ assert(foundEnd);\r
+\r
+ return StrtabContents + Sym->st_name;\r
+}\r
+\r
//\r
// Elf functions interface implementation\r
//\r
mCoffOffset += sizeof (EFI_IMAGE_NT_HEADERS64);\r
break;\r
default:\r
- VerboseMsg ("%s unknown e_machine type. Assume X64", (UINTN)mEhdr->e_machine);\r
+ VerboseMsg ("%s unknown e_machine type %hu. Assume X64", mInImageName, mEhdr->e_machine);\r
mCoffOffset += sizeof (EFI_IMAGE_NT_HEADERS64);\r
break;\r
}\r
}\r
}\r
\r
+ //\r
+ // Move the PE/COFF header right before the first section. This will help us\r
+ // save space when converting to TE.\r
+ //\r
+ if (mCoffAlignment > mCoffOffset) {\r
+ mNtHdrOffset += mCoffAlignment - mCoffOffset;\r
+ mTableOffset += mCoffAlignment - mCoffOffset;\r
+ mCoffOffset = mCoffAlignment;\r
+ }\r
+\r
//\r
// First text sections.\r
//\r
if ((shdr->sh_addr & (shdr->sh_addralign - 1)) == 0) {\r
// if the section address is aligned we must align PE/COFF\r
mCoffOffset = (UINT32) ((mCoffOffset + shdr->sh_addralign - 1) & ~(shdr->sh_addralign - 1));\r
- } else if ((shdr->sh_addr % shdr->sh_addralign) != (mCoffOffset % shdr->sh_addralign)) {\r
- // ARM RVCT tools have behavior outside of the ELF specification to try\r
- // and make images smaller. If sh_addr is not aligned to sh_addralign\r
- // then the section needs to preserve sh_addr MOD sh_addralign.\r
- // Normally doing nothing here works great.\r
- Error (NULL, 0, 3000, "Invalid", "Unsupported section alignment.");\r
+ } else {\r
+ Error (NULL, 0, 3000, "Invalid", "Section address not aligned to its own alignment.");\r
}\r
}\r
\r
assert (FALSE);\r
}\r
\r
- mDebugOffset = mCoffOffset;\r
-\r
- if (mEhdr->e_machine != EM_ARM) {\r
- mCoffOffset = CoffAlign(mCoffOffset);\r
- }\r
+ mDebugOffset = DebugRvaAlign(mCoffOffset);\r
+ mCoffOffset = CoffAlign(mCoffOffset);\r
\r
if (SectionCount > 1 && mOutImageType == FW_EFI_IMAGE) {\r
Warning (NULL, 0, 0, NULL, "Mulitple sections in %s are merged into 1 text section. Source level debug might not work correctly.", mInImageName);\r
if ((shdr->sh_addr & (shdr->sh_addralign - 1)) == 0) {\r
// if the section address is aligned we must align PE/COFF\r
mCoffOffset = (UINT32) ((mCoffOffset + shdr->sh_addralign - 1) & ~(shdr->sh_addralign - 1));\r
- } else if ((shdr->sh_addr % shdr->sh_addralign) != (mCoffOffset % shdr->sh_addralign)) {\r
- // ARM RVCT tools have behavior outside of the ELF specification to try\r
- // and make images smaller. If sh_addr is not aligned to sh_addralign\r
- // then the section needs to preserve sh_addr MOD sh_addralign.\r
- // Normally doing nothing here works great.\r
- Error (NULL, 0, 3000, "Invalid", "Unsupported section alignment.");\r
+ } else {\r
+ Error (NULL, 0, 3000, "Invalid", "Section address not aligned to its own alignment.");\r
}\r
}\r
\r
// section alignment.\r
//\r
if (SectionCount > 0) {\r
- mDebugOffset = mCoffOffset;\r
+ mDebugOffset = DebugRvaAlign(mCoffOffset);\r
}\r
mCoffOffset = mDebugOffset + sizeof(EFI_IMAGE_DEBUG_DIRECTORY_ENTRY) +\r
sizeof(EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY) +\r
if ((shdr->sh_addr & (shdr->sh_addralign - 1)) == 0) {\r
// if the section address is aligned we must align PE/COFF\r
mCoffOffset = (UINT32) ((mCoffOffset + shdr->sh_addralign - 1) & ~(shdr->sh_addralign - 1));\r
- } else if ((shdr->sh_addr % shdr->sh_addralign) != (mCoffOffset % shdr->sh_addralign)) {\r
- // ARM RVCT tools have behavior outside of the ELF specification to try\r
- // and make images smaller. If sh_addr is not aligned to sh_addralign\r
- // then the section needs to preserve sh_addr MOD sh_addralign.\r
- // Normally doing nothing here works great.\r
- Error (NULL, 0, 3000, "Invalid", "Unsupported section alignment.");\r
+ } else {\r
+ Error (NULL, 0, 3000, "Invalid", "Section address not aligned to its own alignment.");\r
}\r
}\r
if (shdr->sh_size != 0) {\r
// header location.\r
//\r
if (Sym->st_shndx == SHN_UNDEF\r
- || Sym->st_shndx == SHN_ABS\r
- || Sym->st_shndx > mEhdr->e_shnum) {\r
- Error (NULL, 0, 3000, "Invalid", "%s bad symbol definition.", mInImageName);\r
+ || Sym->st_shndx >= mEhdr->e_shnum) {\r
+ const UINT8 *SymName = GetSymName(Sym);\r
+ if (SymName == NULL) {\r
+ SymName = (const UINT8 *)"<unknown>";\r
+ }\r
+\r
+ Error (NULL, 0, 3000, "Invalid",\r
+ "%s: Bad definition for symbol '%s'@%#llx or unsupported symbol type. "\r
+ "For example, absolute and undefined symbols are not supported.",\r
+ mInImageName, SymName, Sym->st_value);\r
+\r
+ exit(EXIT_FAILURE);\r
}\r
SymShdr = GetShdrByIndex(Sym->st_shndx);\r
\r
}\r
} else if (mEhdr->e_machine == EM_AARCH64) {\r
\r
- // AARCH64 GCC uses RELA relocation, so all relocations have to be fixed up.\r
- // As opposed to ARM32 using REL.\r
-\r
switch (ELF_R_TYPE(Rel->r_info)) {\r
\r
- case R_AARCH64_ADR_PREL_LO21:\r
- if (Rel->r_addend != 0 ) { /* TODO */\r
- Error (NULL, 0, 3000, "Invalid", "AArch64: R_AARCH64_ADR_PREL_LO21 Need to fixup with addend!.");\r
+ case R_AARCH64_ADR_PREL_PG_HI21:\r
+ case R_AARCH64_ADD_ABS_LO12_NC:\r
+ case R_AARCH64_LDST8_ABS_LO12_NC:\r
+ case R_AARCH64_LDST16_ABS_LO12_NC:\r
+ case R_AARCH64_LDST32_ABS_LO12_NC:\r
+ case R_AARCH64_LDST64_ABS_LO12_NC:\r
+ case R_AARCH64_LDST128_ABS_LO12_NC:\r
+ //\r
+ // AArch64 PG_H21 relocations are typically paired with ABS_LO12\r
+ // relocations, where a PC-relative reference with +/- 4 GB range is\r
+ // split into a relative high part and an absolute low part. Since\r
+ // the absolute low part represents the offset into a 4 KB page, we\r
+ // have to make sure that the 4 KB relative offsets of both the\r
+ // section containing the reference as well as the section to which\r
+ // it refers have not been changed during PE/COFF conversion (i.e.,\r
+ // in ScanSections64() above).\r
+ //\r
+ if (((SecShdr->sh_addr ^ SecOffset) & 0xfff) != 0 ||\r
+ ((SymShdr->sh_addr ^ mCoffSectionsOffset[Sym->st_shndx]) & 0xfff) != 0 ||\r
+ mCoffAlignment < 0x1000) {\r
+ Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s AARCH64 small code model requires 4 KB section alignment.",\r
+ mInImageName);\r
+ break;\r
}\r
- break;\r
+ /* fall through */\r
\r
+ case R_AARCH64_ADR_PREL_LO21:\r
case R_AARCH64_CONDBR19:\r
- if (Rel->r_addend != 0 ) { /* TODO */\r
- Error (NULL, 0, 3000, "Invalid", "AArch64: R_AARCH64_CONDBR19 Need to fixup with addend!.");\r
- }\r
- break;\r
-\r
case R_AARCH64_LD_PREL_LO19:\r
- if (Rel->r_addend != 0 ) { /* TODO */\r
- Error (NULL, 0, 3000, "Invalid", "AArch64: R_AARCH64_LD_PREL_LO19 Need to fixup with addend!.");\r
- }\r
- break;\r
-\r
case R_AARCH64_CALL26:\r
case R_AARCH64_JUMP26:\r
- if (Rel->r_addend != 0 ) {\r
- // Some references to static functions sometime start at the base of .text + addend.\r
- // It is safe to ignore these relocations because they patch a `BL` instructions that\r
- // contains an offset from the instruction itself and there is only a single .text section.\r
- // So we check if the symbol is a "section symbol"\r
- if (ELF64_ST_TYPE (Sym->st_info) == STT_SECTION) {\r
- break;\r
- }\r
- Error (NULL, 0, 3000, "Invalid", "AArch64: R_AARCH64_JUMP26 Need to fixup with addend!.");\r
+ case R_AARCH64_PREL64:\r
+ case R_AARCH64_PREL32:\r
+ case R_AARCH64_PREL16:\r
+ //\r
+ // The GCC toolchains (i.e., binutils) may corrupt section relative\r
+ // relocations when emitting relocation sections into fully linked\r
+ // binaries. More specifically, they tend to fail to take into\r
+ // account the fact that a '.rodata + XXX' relocation needs to have\r
+ // its addend recalculated once .rodata is merged into the .text\r
+ // section, and the relocation emitted into the .rela.text section.\r
+ //\r
+ // We cannot really recover from this loss of information, so the\r
+ // only workaround is to prevent having to recalculate any relative\r
+ // relocations at all, by using a linker script that ensures that\r
+ // the offset between the Place and the Symbol is the same in both\r
+ // the ELF and the PE/COFF versions of the binary.\r
+ //\r
+ if ((SymShdr->sh_addr - SecShdr->sh_addr) !=\r
+ (mCoffSectionsOffset[Sym->st_shndx] - SecOffset)) {\r
+ Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s AARCH64 relative relocations require identical ELF and PE/COFF section offsets",\r
+ mInImageName);\r
}\r
break;\r
\r
- case R_AARCH64_ADR_PREL_PG_HI21:\r
- // TODO : AArch64 'small' memory model.\r
- Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupported ELF EM_AARCH64 relocation R_AARCH64_ADR_PREL_PG_HI21.", mInImageName);\r
- break;\r
-\r
- case R_AARCH64_ADD_ABS_LO12_NC:\r
- // TODO : AArch64 'small' memory model.\r
- Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupported ELF EM_AARCH64 relocation R_AARCH64_ADD_ABS_LO12_NC.", mInImageName);\r
- break;\r
-\r
// Absolute relocations.\r
case R_AARCH64_ABS64:\r
*(UINT64 *)Targ = *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx];\r
Error (NULL, 0, 3000, "Invalid", "%s unsupported ELF EM_X86_64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE(Rel->r_info));\r
}\r
} else if (mEhdr->e_machine == EM_AARCH64) {\r
- // AArch64 GCC uses RELA relocation, so all relocations has to be fixed up. ARM32 uses REL.\r
+\r
switch (ELF_R_TYPE(Rel->r_info)) {\r
case R_AARCH64_ADR_PREL_LO21:\r
- break;\r
-\r
case R_AARCH64_CONDBR19:\r
- break;\r
-\r
case R_AARCH64_LD_PREL_LO19:\r
- break;\r
-\r
case R_AARCH64_CALL26:\r
- break;\r
-\r
case R_AARCH64_JUMP26:\r
- break;\r
-\r
+ case R_AARCH64_PREL64:\r
+ case R_AARCH64_PREL32:\r
+ case R_AARCH64_PREL16:\r
case R_AARCH64_ADR_PREL_PG_HI21:\r
- // TODO : AArch64 'small' memory model.\r
- Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s unsupported ELF EM_AARCH64 relocation R_AARCH64_ADR_PREL_PG_HI21.", mInImageName);\r
- break;\r
-\r
case R_AARCH64_ADD_ABS_LO12_NC:\r
- // TODO : AArch64 'small' memory model.\r
- Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s unsupported ELF EM_AARCH64 relocation R_AARCH64_ADD_ABS_LO12_NC.", mInImageName);\r
+ case R_AARCH64_LDST8_ABS_LO12_NC:\r
+ case R_AARCH64_LDST16_ABS_LO12_NC:\r
+ case R_AARCH64_LDST32_ABS_LO12_NC:\r
+ case R_AARCH64_LDST64_ABS_LO12_NC:\r
+ case R_AARCH64_LDST128_ABS_LO12_NC:\r
+ //\r
+ // No fixups are required for relative relocations, provided that\r
+ // the relative offsets between sections have been preserved in\r
+ // the ELF to PE/COFF conversion. We have already asserted that\r
+ // this is the case in WriteSections64 ().\r
+ //\r
break;\r
\r
case R_AARCH64_ABS64:\r
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