Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
Portions copyright (c) 2013-2014, ARM Ltd. All rights reserved.<BR>\r
\r
-This program and the accompanying materials are licensed and made available\r
-under the terms and conditions of the BSD License which accompanies this\r
-distribution. The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
);\r
\r
//\r
-// Rename ELF32 strucutres to common names to help when porting to ELF64.\r
+// Rename ELF32 structures to common names to help when porting to ELF64.\r
//\r
typedef Elf64_Shdr Elf_Shdr;\r
typedef Elf64_Ehdr Elf_Ehdr;\r
mNtHdrOffset = mCoffOffset;\r
switch (mEhdr->e_machine) {\r
case EM_X86_64:\r
- case EM_IA_64:\r
case EM_AARCH64:\r
mCoffOffset += sizeof (EFI_IMAGE_NT_HEADERS64);\r
break;\r
mCoffOffset = CoffAlign(mCoffOffset);\r
\r
if (SectionCount > 1 && mOutImageType == FW_EFI_IMAGE) {\r
- Warning (NULL, 0, 0, NULL, "Mulitple sections in %s are merged into 1 text section. Source level debug might not work correctly.", mInImageName);\r
+ Warning (NULL, 0, 0, NULL, "Multiple sections in %s are merged into 1 text section. Source level debug might not work correctly.", mInImageName);\r
}\r
\r
//\r
}\r
\r
if (SectionCount > 1 && mOutImageType == FW_EFI_IMAGE) {\r
- Warning (NULL, 0, 0, NULL, "Mulitple sections in %s are merged into 1 data section. Source level debug might not work correctly.", mInImageName);\r
+ Warning (NULL, 0, 0, NULL, "Multiple sections in %s are merged into 1 data section. Source level debug might not work correctly.", mInImageName);\r
}\r
\r
//\r
NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_X64;\r
NtHdr->Pe32Plus.OptionalHeader.Magic = EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;\r
break;\r
- case EM_IA_64:\r
- NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_IPF;\r
- NtHdr->Pe32Plus.OptionalHeader.Magic = EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;\r
- break;\r
case EM_AARCH64:\r
NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_AARCH64;\r
NtHdr->Pe32Plus.OptionalHeader.Magic = EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;\r
\r
default:\r
//\r
- // Ignore for unkown section type.\r
+ // Ignore for unknown section type.\r
//\r
- VerboseMsg ("%s unknown section type %x. We directly copy this section into Coff file", mInImageName, (unsigned)Shdr->sh_type);\r
+ VerboseMsg ("%s unknown section type %x. We ignore this unknown section type.", mInImageName, (unsigned)Shdr->sh_type);\r
break;\r
}\r
}\r
} else if (mEhdr->e_machine == EM_AARCH64) {\r
\r
switch (ELF_R_TYPE(Rel->r_info)) {\r
+ INT64 Offset;\r
+\r
+ case R_AARCH64_LD64_GOT_LO12_NC:\r
+ //\r
+ // Convert into an ADD instruction - see R_AARCH64_ADR_GOT_PAGE below.\r
+ //\r
+ *(UINT32 *)Targ &= 0x3ff;\r
+ *(UINT32 *)Targ |= 0x91000000 | ((Sym->st_value & 0xfff) << 10);\r
+ break;\r
+\r
+ case R_AARCH64_ADR_GOT_PAGE:\r
+ //\r
+ // This relocation points to the GOT entry that contains the absolute\r
+ // address of the symbol we are referring to. Since EDK2 only uses\r
+ // fully linked binaries, we can avoid the indirection, and simply\r
+ // refer to the symbol directly. This implies having to patch the\r
+ // subsequent LDR instruction (covered by a R_AARCH64_LD64_GOT_LO12_NC\r
+ // relocation) into an ADD instruction - this is handled above.\r
+ //\r
+ Offset = (Sym->st_value - (Rel->r_offset & ~0xfff)) >> 12;\r
+\r
+ *(UINT32 *)Targ &= 0x9000001f;\r
+ *(UINT32 *)Targ |= ((Offset & 0x1ffffc) << (5 - 2)) | ((Offset & 0x3) << 29);\r
+\r
+ /* fall through */\r
\r
case R_AARCH64_ADR_PREL_PG_HI21:\r
+ //\r
+ // In order to handle Cortex-A53 erratum #843419, the LD linker may\r
+ // convert ADRP instructions into ADR instructions, but without\r
+ // updating the static relocation type, and so we may end up here\r
+ // while the instruction in question is actually ADR. So let's\r
+ // just disregard it: the section offset check we apply below to\r
+ // ADR instructions will trigger for its R_AARCH64_xxx_ABS_LO12_NC\r
+ // companion instruction as well, so it is safe to omit it here.\r
+ //\r
+ if ((*(UINT32 *)Targ & BIT31) == 0) {\r
+ break;\r
+ }\r
+\r
//\r
// AArch64 PG_H21 relocations are typically paired with ABS_LO12\r
// relocations, where a PC-relative reference with +/- 4 GB range is\r
// Attempt to convert the ADRP into an ADR instruction.\r
// This is only possible if the symbol is within +/- 1 MB.\r
//\r
- INT64 Offset;\r
\r
// Decode the ADRP instruction\r
Offset = (INT32)((*(UINT32 *)Targ & 0xffffe0) << 8);\r
+ (Rel->r_offset - SecShdr->sh_addr)),\r
EFI_IMAGE_REL_BASED_DIR64);\r
break;\r
- case R_X86_64_32S:\r
+ //\r
+ // R_X86_64_32 and R_X86_64_32S are ELF64 relocations emitted when using\r
+ // the SYSV X64 ABI small non-position-independent code model.\r
+ // R_X86_64_32 is used for unsigned 32-bit immediates with a 32-bit operand\r
+ // size. The value is either not extended, or zero-extended to 64 bits.\r
+ // R_X86_64_32S is used for either signed 32-bit non-rip-relative displacements\r
+ // or signed 32-bit immediates with a 64-bit operand size. The value is\r
+ // sign-extended to 64 bits.\r
+ // EFI_IMAGE_REL_BASED_HIGHLOW is a PE relocation that uses 32-bit arithmetic\r
+ // for rebasing an image.\r
+ // EFI PE binaries declare themselves EFI_IMAGE_FILE_LARGE_ADDRESS_AWARE and\r
+ // may load above 2GB. If an EFI PE binary with a converted R_X86_64_32S\r
+ // relocation is loaded above 2GB, the value will get sign-extended to the\r
+ // negative part of the 64-bit address space. The negative part of the 64-bit\r
+ // address space is unmapped, so accessing such an address page-faults.\r
+ // In order to support R_X86_64_32S, it is necessary to unset\r
+ // EFI_IMAGE_FILE_LARGE_ADDRESS_AWARE, and the EFI PE loader must implement\r
+ // this flag and abstain from loading such a PE binary above 2GB.\r
+ // Since this feature is not supported, support for R_X86_64_32S (and hence\r
+ // the small non-position-independent code model) is disabled.\r
+ //\r
+ // case R_X86_64_32S:\r
case R_X86_64_32:\r
VerboseMsg ("EFI_IMAGE_REL_BASED_HIGHLOW Offset: 0x%08X",\r
mCoffSectionsOffset[RelShdr->sh_info] + (Rel->r_offset - SecShdr->sh_addr));\r
case R_AARCH64_LDST32_ABS_LO12_NC:\r
case R_AARCH64_LDST64_ABS_LO12_NC:\r
case R_AARCH64_LDST128_ABS_LO12_NC:\r
+ case R_AARCH64_ADR_GOT_PAGE:\r
+ case R_AARCH64_LD64_GOT_LO12_NC:\r
//\r
// No fixups are required for relative relocations, provided that\r
// the relative offsets between sections have been preserved in\r
projects / mirror_edk2.git / blobdiff