/** @file\r
Support for PCI 2.2 standard.\r
\r
- Copyright (c) 2006 - 2008, Intel Corporation All rights reserved.\r
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
\r
This program and the accompanying materials are licensed and made available\r
under the terms and conditions of the BSD License which accompanies this\r
- distribution. The full text of the license may be found at:\r
- http://opensource.org/licenses/bsd-license.php\r
+ distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
- File Name: pci22.h\r
-\r
**/\r
\r
#ifndef _PCI22_H\r
#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80\r
#define PCI_CLASS_ISA_POSITIVE_DECODE 0x80 // obsolete\r
\r
-#define PCI_CLASS_SCC 0x07 // Simple communications controllers \r
+#define PCI_CLASS_SCC 0x07 // Simple communications controllers\r
#define PCI_SUBCLASS_SERIAL 0x00\r
#define PCI_IF_GENERIC_XT 0x00\r
#define PCI_IF_16450 0x01\r
#define PCI_IF_8259_PIC 0x00\r
#define PCI_IF_ISA_PIC 0x01\r
#define PCI_IF_EISA_PIC 0x02\r
-#define PCI_IF_APIC_CONTROLLER 0x10 // I/O APIC interrupt controller , 32 bye none-prefectable memory. \r
-#define PCI_IF_APIC_CONTROLLER2 0x20 \r
+#define PCI_IF_APIC_CONTROLLER 0x10 // I/O APIC interrupt controller , 32 bye none-prefectable memory.\r
+#define PCI_IF_APIC_CONTROLLER2 0x20\r
#define PCI_SUBCLASS_TIMER 0x02\r
#define PCI_IF_8254_TIMER 0x00\r
#define PCI_IF_ISA_TIMER 0x01\r
\r
#define PCI_SECURITY_CONTROLLER 0x10 // Encryption and decryption controller\r
#define PCI_SUBCLASS_NET_COMPUT 0x00\r
-#define PCI_SUBCLASS_ENTERTAINMENT 0x10 \r
+#define PCI_SUBCLASS_ENTERTAINMENT 0x10\r
\r
#define PCI_CLASS_DPIO 0x11\r
\r
#pragma pack()\r
\r
#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55\r
-#define PCI_DATA_STRUCTURE_SIGNATURE EFI_SIGNATURE_32 ('P', 'C', 'I', 'R')\r
+#define PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R')\r
#define PCI_CODE_TYPE_PCAT_IMAGE 0x00\r
#define PCI_CODE_TYPE_EFI_IMAGE 0x03\r
#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001\r