Adding support for BeagleBoard.

[mirror_edk2.git] / BeagleBoardPkg / Sec / Arm / ModuleEntryPoint.asm

diff --git a/BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.asm b/BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.asm
new file mode 100755 (executable)
index 0000000..fb30e4d
--- /dev/null
+++ b/BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.asm
@@ -0,0 +1,95 @@
+//------------------------------------------------------------------------------ \r
+//\r
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.\r
+//\r
+// All rights reserved. This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution.  The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//------------------------------------------------------------------------------\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <AutoGen.h>\r
+  INCLUDE AsmMacroIoLib.inc\r
+  \r
+  IMPORT  CEntryPoint\r
+  EXPORT  _ModuleEntryPoint\r
+        \r
+  PRESERVE8\r
+  AREA    ModuleEntryPoint, CODE, READONLY\r
+  \r
+\r
+_ModuleEntryPoint\r
+ \r
+  //Disable L2 cache\r
+  mrc     p15, 0, r0, c1, c0, 1   // read Auxiliary Control Register\r
+  bic     r0, r0, #0x00000002     // disable L2 cache\r
+  mcr     p15, 0, r0, c1, c0, 1   // store Auxiliary Control Register\r
+  \r
+  //Enable Strict alignment checking & Instruction cache\r
+  mrc     p15, 0, r0, c1, c0, 0\r
+  bic     r0, r0, #0x00002300     /* clear bits 13, 9:8 (--V- --RS) */\r
+  bic     r0, r0, #0x00000005     /* clear bits 0, 2 (---- -C-M) */\r
+  orr     r0, r0, #0x00000002     /* set bit 1 (A) Align */\r
+  orr     r0, r0, #0x00001000     /* set bit 12 (I) enable I-Cache */\r
+  mcr     p15, 0, r0, c1, c0, 0\r
+ \r
+  // Set CPU vectors to start of DRAM\r
+  mov     r0, #0x80000000\r
+  mcr     p15, 0, r0, c12, c0, 0\r
+  /* before we call C code, lets setup the stack pointer in internal RAM*/\r
+stack_pointer_setup\r
+\r
+  //\r
+  // Set stack based on PCD values. Need to do it this way to make C code work \r
+  // when it runs from FLASH. \r
+  //  \r
+  LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2)    /* stack base arg2  */\r
+  LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3)    /* stack size arg3  */\r
+  add     r4, r2, r3\r
+\r
+  //Enter IRQ mode and set up IRQ stack pointer\r
+  mov     r0,#0x12|0x80|0x40\r
+  msr     CPSR_c,r0\r
+  mov     r13,r4\r
+\r
+  //Enter Abort mode and set up Abort stack pointer\r
+  mov     r0,#0x17|0x80|0x40\r
+  msr     CPSR_c,r0\r
+  sub     r4, r4, #0x400\r
+  mov     r13,r4\r
+\r
+  //Enter Undefined mode and set up Undefined stack pointer\r
+  mov     r0,#0x1b|0x80|0x40\r
+  msr     CPSR_c,r0\r
+  sub     r4, r4, #0x400\r
+  mov     r13,r4\r
+\r
+  //Enter SVC mode and set up SVC stack pointer\r
+  mov     r0,#0x13|0x80|0x40\r
+  msr     CPSR_c,r0\r
+  sub     r4, r4, #0x400\r
+  mov     r13,r4\r
+\r
+  //Enter System mode and set up System stack pointer\r
+  mov     r0,#0x1f|0x80|0x40\r
+  msr     CPSR_c,r0\r
+  sub     r4, r4, #0x400\r
+  mov     r13,r4\r
+\r
+  // Call C entry point\r
+  mov     r0, #0x80000000   /* memory base arg0          */\r
+  mov     r1, #0x08000000   /* memory size arg1          */\r
+  blx     CEntryPoint       /* Assume C code is thumb    */\r
+\r
+ShouldNeverGetHere\r
+  /* _CEntryPoint should never return */\r
+  b       ShouldNeverGetHere\r
+  \r
+  END\r
+\r