CorebootPayloadPkg/PciHostBridgeLib: clear aperture vars for (re)init

[mirror_edk2.git] / CorebootPayloadPkg / Library / PciHostBridgeLib / PciHostBridgeSupport.c

diff --git a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
index a95ffcaf64906813d4af9520610a6d5498168c97..18dcbafdf0c6776e5d6bc192580c0dc88d8842e1 100644 (file)
--- a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
+++ b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
@@ -91,7 +91,7 @@ AdjustRootBridgeResource (
   // Align IO  resource at 4K  boundary\r
   //\r
   Mask        = 0xFFFULL;\r
-  Io->Limit   = (Io->Limit + Mask) & ~Mask;\r
+  Io->Limit   = ((Io->Limit + Mask) & ~Mask) - 1;\r
   if (Io->Base != MAX_UINT64) {\r
     Io->Base &= ~Mask;\r
   }\r
@@ -100,7 +100,7 @@ AdjustRootBridgeResource (
   // Align MEM resource at 1MB boundary\r
   //\r
   Mask        = 0xFFFFFULL;\r
-  Mem->Limit  = (Mem->Limit + Mask) & ~Mask;\r
+  Mem->Limit  = ((Mem->Limit + Mask) & ~Mask) - 1;\r
   if (Mem->Base != MAX_UINT64) {\r
     Mem->Base &= ~Mask;\r
   }\r
@@ -193,6 +193,7 @@ PcatPciRootBridgeParseBars (
   UINT32                            UpperValue;\r
   UINT64                            Mask;\r
   UINTN                             Offset;\r
+  UINTN                             LowBit;\r
   UINT64                            Base;\r
   UINT64                            Length;\r
   UINT64                            Limit;\r
@@ -262,7 +263,10 @@ PcatPciRootBridgeParseBars (
 \r
           Base = Base | LShiftU64 ((UINT64) OriginalUpperValue, 32);\r
           Length = Length | LShiftU64 ((UINT64) UpperValue, 32);\r
-          Length = (~Length) + 1;\r
+          if (Length != 0) {\r
+            LowBit = LowBitSet64 (Length);\r
+            Length = LShiftU64 (1ULL, LowBit);\r
+          }\r
 \r
           if ((Value & BIT3) == BIT3) {\r
             MemAperture = PMemAbove4G;\r
@@ -324,8 +328,13 @@ ScanForRootBridges (
   for (PrimaryBus = 0; PrimaryBus <= PCI_MAX_BUS; PrimaryBus = SubBus + 1) {\r
     SubBus = PrimaryBus;\r
     Attributes = 0;\r
+\r
+    ZeroMem (&Io, sizeof (Io));\r
+    ZeroMem (&Mem, sizeof (Mem));\r
+    ZeroMem (&MemAbove4G, sizeof (MemAbove4G));\r
+    ZeroMem (&PMem, sizeof (PMem));\r
+    ZeroMem (&PMemAbove4G, sizeof (PMemAbove4G));\r
     Io.Base = Mem.Base = MemAbove4G.Base = PMem.Base = PMemAbove4G.Base = MAX_UINT64;\r
-    Io.Limit = Mem.Limit = MemAbove4G.Limit = PMem.Limit = PMemAbove4G.Limit = 0;\r
     //\r
     // Scan all the PCI devices on the primary bus of the PCI root bridge\r
     //\r