DuetPkg: Remove DuetPkg

[mirror_edk2.git] / DuetPkg / DxeIpl / X64 / VirtualMemory.h

diff --git a/DuetPkg/DxeIpl/X64/VirtualMemory.h b/DuetPkg/DxeIpl/X64/VirtualMemory.h
deleted file mode 100644 (file)
index 204f04e..0000000
--- a/DuetPkg/DxeIpl/X64/VirtualMemory.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/** @file\r
-\r
-Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials                          \r
-are licensed and made available under the terms and conditions of the BSD License         \r
-which accompanies this distribution.  The full text of the license may be found at        \r
-http://opensource.org/licenses/bsd-license.php                                            \r
-                                                                                          \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
-\r
-Module Name:\r
-  VirtualMemory.h\r
-\r
-Abstract:\r
-\r
-Revision History:\r
-\r
-**/\r
-  \r
-#ifndef _VIRTUAL_MEMORY_H_\r
-#define _VIRTUAL_MEMORY_H_\r
-\r
-#pragma pack(1)\r
-\r
-//\r
-// Page Map Level 4 Offset (PML4) and\r
-// Page Directory Pointer Table (PDPE) entries 4K & 2M\r
-//\r
-\r
-typedef union {\r
-  struct {\r
-    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
-    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
-    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
-    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
-    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
-    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
-    UINT64  Reserved:1;               // Reserved\r
-    UINT64  MustBeZero:2;             // Must Be Zero\r
-    UINT64  Available:3;              // Available for use by system software\r
-    UINT64  PageTableBaseAddress:40;  // Page Table Base Address\r
-    UINT64  AvabilableHigh:11;        // Available for use by system software\r
-    UINT64  Nx:1;                     // No Execute bit\r
-  } Bits;\r
-  UINT64    Uint64;\r
-} X64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K;\r
-\r
-//\r
-// Page Directory Entry 4K\r
-//\r
-typedef union {\r
-  struct {\r
-    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
-    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
-    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
-    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
-    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
-    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
-    UINT64  MustBeZero:3;             // Must Be Zero\r
-    UINT64  Available:3;              // Available for use by system software\r
-    UINT64  PageTableBaseAddress:40;  // Page Table Base Address\r
-    UINT64  AvabilableHigh:11;        // Available for use by system software\r
-    UINT64  Nx:1;                     // No Execute bit\r
-  } Bits;\r
-  UINT64    Uint64;\r
-} X64_PAGE_DIRECTORY_ENTRY_4K;\r
-\r
-//\r
-// Page Table Entry 4K\r
-//\r
-typedef union {\r
-  struct {\r
-    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
-    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
-    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
-    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
-    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
-    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
-    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page\r
-    UINT64  PAT:1;                    // 0 = Ignore Page Attribute Table \r
-    UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
-    UINT64  Available:3;              // Available for use by system software\r
-    UINT64  PageTableBaseAddress:40;  // Page Table Base Address\r
-    UINT64  AvabilableHigh:11;        // Available for use by system software\r
-    UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution\r
-  } Bits;\r
-  UINT64    Uint64;\r
-} X64_PAGE_TABLE_ENTRY_4K;\r
-\r
-//\r
-// Page Table Entry 2M\r
-//\r
-typedef union {\r
-  struct {\r
-    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
-    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
-    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
-    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
-    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
-    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
-    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page\r
-    UINT64  MustBe1:1;                // Must be 1 \r
-    UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
-    UINT64  Available:3;              // Available for use by system software\r
-    UINT64  PAT:1;                    //\r
-    UINT64  MustBeZero:8;             // Must be zero;\r
-    UINT64  PageTableBaseAddress:31;  // Page Table Base Address\r
-    UINT64  AvabilableHigh:11;        // Available for use by system software\r
-    UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution\r
-  } Bits;\r
-  UINT64    Uint64;\r
-} X64_PAGE_TABLE_ENTRY_2M;\r
-\r
-#pragma pack()\r
-\r
-#endif \r