+++ /dev/null
-/*++\r
-\r
-Copyright (c) 2005 - 2009, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-\r
-Module Name:\r
- PcatPciRootBridge.c\r
- \r
-Abstract:\r
-\r
- EFI PC-AT PCI Root Bridge Controller\r
-\r
---*/\r
-\r
-#include "PcatPciRootBridge.h"\r
-#include "DeviceIo.h"\r
-\r
-EFI_CPU_IO2_PROTOCOL *gCpuIo;\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-InitializePcatPciRootBridge (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
- )\r
-/*++\r
-\r
-Routine Description:\r
- Initializes the PCI Root Bridge Controller\r
-\r
-Arguments:\r
- ImageHandle -\r
- SystemTable -\r
- \r
-Returns:\r
- None\r
-\r
---*/\r
-{\r
- EFI_STATUS Status;\r
- PCAT_PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
- UINTN PciSegmentIndex;\r
- UINTN PciRootBridgeIndex;\r
- UINTN PrimaryBusIndex;\r
- UINTN NumberOfPciRootBridges;\r
- UINTN NumberOfPciDevices;\r
- UINTN Device;\r
- UINTN Function;\r
- UINT16 VendorId;\r
- PCI_TYPE01 PciConfigurationHeader;\r
- UINT64 Address;\r
- UINT64 Value;\r
- UINT64 Base;\r
- UINT64 Limit;\r
-\r
- //\r
- // Initialize gCpuIo now since the chipset init code requires it.\r
- //\r
- Status = gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL, (VOID **)&gCpuIo);\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- //\r
- // Initialize variables required to search all PCI segments for PCI devices\r
- //\r
- PciSegmentIndex = 0;\r
- PciRootBridgeIndex = 0;\r
- NumberOfPciRootBridges = 0;\r
- PrimaryBusIndex = 0;\r
-\r
- while (PciSegmentIndex <= PCI_MAX_SEGMENT) {\r
-\r
- PrivateData = NULL;\r
- Status = gBS->AllocatePool(\r
- EfiBootServicesData,\r
- sizeof (PCAT_PCI_ROOT_BRIDGE_INSTANCE),\r
- (VOID **)&PrivateData\r
- );\r
- if (EFI_ERROR (Status)) {\r
- goto Done;\r
- }\r
-\r
- ZeroMem (PrivateData, sizeof (PCAT_PCI_ROOT_BRIDGE_INSTANCE));\r
-\r
- //\r
- // Initialize the signature of the private data structure\r
- //\r
- PrivateData->Signature = PCAT_PCI_ROOT_BRIDGE_SIGNATURE;\r
- PrivateData->Handle = NULL;\r
- PrivateData->DevicePath = NULL;\r
- InitializeListHead (&PrivateData->MapInfo);\r
-\r
- //\r
- // Initialize the PCI root bridge number and the bus range for that root bridge\r
- //\r
- PrivateData->RootBridgeNumber = (UINT32)PciRootBridgeIndex;\r
- PrivateData->PrimaryBus = (UINT32)PrimaryBusIndex;\r
- PrivateData->SubordinateBus = (UINT32)PrimaryBusIndex;\r
-\r
- PrivateData->IoBase = 0xffffffff;\r
- PrivateData->MemBase = 0xffffffff;\r
- PrivateData->Mem32Base = 0xffffffffffffffffULL;\r
- PrivateData->Pmem32Base = 0xffffffffffffffffULL;\r
- PrivateData->Mem64Base = 0xffffffffffffffffULL;\r
- PrivateData->Pmem64Base = 0xffffffffffffffffULL;\r
-\r
- //\r
- // The default mechanism for performing PCI Configuration cycles is to \r
- // use the I/O ports at 0xCF8 and 0xCFC. This is only used for IA-32.\r
- // IPF uses SAL calls to perform PCI COnfiguration cycles\r
- //\r
- PrivateData->PciAddress = 0xCF8;\r
- PrivateData->PciData = 0xCFC;\r
-\r
- //\r
- // Get the physical I/O base for performing PCI I/O cycles\r
- // For IA-32, this is always 0, because IA-32 has IN and OUT instructions\r
- // For IPF, a SAL call is made to retrieve the base address for PCI I/O cycles\r
- //\r
- Status = PcatRootBridgeIoGetIoPortMapping (\r
- &PrivateData->PhysicalIoBase, \r
- &PrivateData->PhysicalMemoryBase\r
- );\r
- if (EFI_ERROR (Status)) {\r
- goto Done;\r
- }\r
-\r
- //\r
- // Get PCI Express Base Address\r
- //\r
- PrivateData->PciExpressBaseAddress = GetPciExpressBaseAddressForRootBridge (PciSegmentIndex, PciRootBridgeIndex);\r
- if (PrivateData->PciExpressBaseAddress != 0) {\r
- DEBUG ((EFI_D_ERROR, "PCIE Base - 0x%lx\n", PrivateData->PciExpressBaseAddress));\r
- }\r
-\r
- //\r
- // Create a lock for performing PCI Configuration cycles\r
- //\r
- EfiInitializeLock (&PrivateData->PciLock, TPL_HIGH_LEVEL);\r
-\r
- //\r
- // Initialize the attributes for this PCI root bridge\r
- //\r
- PrivateData->Attributes = 0;\r
-\r
- //\r
- // Build the EFI Device Path Protocol instance for this PCI Root Bridge\r
- //\r
- Status = PcatRootBridgeDevicePathConstructor (&PrivateData->DevicePath, PciRootBridgeIndex, (BOOLEAN)((PrivateData->PciExpressBaseAddress != 0) ? TRUE : FALSE));\r
- if (EFI_ERROR (Status)) {\r
- goto Done;\r
- }\r
-\r
- //\r
- // Build the PCI Root Bridge I/O Protocol instance for this PCI Root Bridge\r
- //\r
- Status = PcatRootBridgeIoConstructor (&PrivateData->Io, PciSegmentIndex);\r
- if (EFI_ERROR (Status)) {\r
- goto Done;\r
- }\r
- \r
- //\r
- // Scan all the PCI devices on the primary bus of the PCI root bridge\r
- //\r
- for (Device = 0, NumberOfPciDevices = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
- \r
- for (Function = 0; Function <= PCI_MAX_FUNC; Function++) {\r
-\r
- //\r
- // Compute the PCI configuration address of the PCI device to probe\r
- //\r
- Address = EFI_PCI_ADDRESS (PrimaryBusIndex, Device, Function, 0);\r
-\r
- //\r
- // Read the Vendor ID from the PCI Configuration Header\r
- //\r
- Status = PrivateData->Io.Pci.Read (\r
- &PrivateData->Io, \r
- EfiPciWidthUint16, \r
- Address, \r
- sizeof (VendorId) / sizeof (UINT16), \r
- &VendorId\r
- );\r
- if ((EFI_ERROR (Status)) || ((VendorId == 0xffff) && (Function == 0))) {\r
- //\r
- // If the PCI Configuration Read fails, or a PCI device does not exist, then \r
- // skip this entire PCI device\r
- //\r
- break;\r
- }\r
- if (VendorId == 0xffff) {\r
- //\r
- // If PCI function != 0, VendorId == 0xFFFF, we continue to search PCI function.\r
- //\r
- continue;\r
- }\r
-\r
- //\r
- // Read the entire PCI Configuration Header\r
- //\r
- Status = PrivateData->Io.Pci.Read (\r
- &PrivateData->Io, \r
- EfiPciWidthUint16, \r
- Address, \r
- sizeof (PciConfigurationHeader) / sizeof (UINT16), \r
- &PciConfigurationHeader\r
- );\r
- if (EFI_ERROR (Status)) {\r
- //\r
- // If the entire PCI Configuration Header can not be read, then skip this entire PCI device\r
- //\r
- break;\r
- }\r
-\r
-\r
- //\r
- // Increment the number of PCI device found on the primary bus of the PCI root bridge\r
- //\r
- NumberOfPciDevices++;\r
-\r
- //\r
- // Look for devices with the VGA Palette Snoop enabled in the COMMAND register of the PCI Config Header\r
- //\r
- if (PciConfigurationHeader.Hdr.Command & 0x20) {\r
- PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
- }\r
-\r
- //\r
- // If the device is a PCI-PCI Bridge, then look at the Subordinate Bus Number\r
- //\r
- if (IS_PCI_BRIDGE(&PciConfigurationHeader)) {\r
- //\r
- // Get the Bus range that the PPB is decoding\r
- //\r
- if (PciConfigurationHeader.Bridge.SubordinateBus > PrivateData->SubordinateBus) {\r
- //\r
- // If the suborinate bus number of the PCI-PCI bridge is greater than the PCI root bridge's\r
- // current subordinate bus number, then update the PCI root bridge's subordinate bus number \r
- //\r
- PrivateData->SubordinateBus = PciConfigurationHeader.Bridge.SubordinateBus;\r
- }\r
-\r
- //\r
- // Get the I/O range that the PPB is decoding\r
- //\r
- Value = PciConfigurationHeader.Bridge.IoBase & 0x0f;\r
- Base = ((UINT32)PciConfigurationHeader.Bridge.IoBase & 0xf0) << 8;\r
- Limit = (((UINT32)PciConfigurationHeader.Bridge.IoLimit & 0xf0) << 8) | 0x0fff;\r
- if (Value == 0x01) {\r
- Base |= ((UINT32)PciConfigurationHeader.Bridge.IoBaseUpper16 << 16);\r
- Limit |= ((UINT32)PciConfigurationHeader.Bridge.IoLimitUpper16 << 16);\r
- }\r
- if (Base < Limit) {\r
- if (PrivateData->IoBase > Base) {\r
- PrivateData->IoBase = Base;\r
- }\r
- if (PrivateData->IoLimit < Limit) {\r
- PrivateData->IoLimit = Limit;\r
- }\r
- }\r
-\r
- //\r
- // Get the Memory range that the PPB is decoding\r
- //\r
- Base = ((UINT32)PciConfigurationHeader.Bridge.MemoryBase & 0xfff0) << 16;\r
- Limit = (((UINT32)PciConfigurationHeader.Bridge.MemoryLimit & 0xfff0) << 16) | 0xfffff;\r
- if (Base < Limit) {\r
- if (PrivateData->MemBase > Base) {\r
- PrivateData->MemBase = Base;\r
- }\r
- if (PrivateData->MemLimit < Limit) {\r
- PrivateData->MemLimit = Limit;\r
- }\r
- if (PrivateData->Mem32Base > Base) {\r
- PrivateData->Mem32Base = Base;\r
- }\r
- if (PrivateData->Mem32Limit < Limit) {\r
- PrivateData->Mem32Limit = Limit;\r
- }\r
- }\r
-\r
- //\r
- // Get the Prefetchable Memory range that the PPB is decoding\r
- //\r
- Value = PciConfigurationHeader.Bridge.PrefetchableMemoryBase & 0x0f;\r
- Base = ((UINT32)PciConfigurationHeader.Bridge.PrefetchableMemoryBase & 0xfff0) << 16;\r
- Limit = (((UINT32)PciConfigurationHeader.Bridge.PrefetchableMemoryLimit & 0xfff0) << 16) | 0xffffff;\r
- if (Value == 0x01) {\r
- Base |= LShiftU64((UINT64)PciConfigurationHeader.Bridge.PrefetchableBaseUpper32,32);\r
- Limit |= LShiftU64((UINT64)PciConfigurationHeader.Bridge.PrefetchableLimitUpper32,32);\r
- }\r
- if (Base < Limit) {\r
- if (PrivateData->MemBase > Base) {\r
- PrivateData->MemBase = Base;\r
- }\r
- if (PrivateData->MemLimit < Limit) {\r
- PrivateData->MemLimit = Limit;\r
- }\r
- if (Value == 0x00) {\r
- if (PrivateData->Pmem32Base > Base) {\r
- PrivateData->Pmem32Base = Base;\r
- }\r
- if (PrivateData->Pmem32Limit < Limit) {\r
- PrivateData->Pmem32Limit = Limit;\r
- }\r
- }\r
- if (Value == 0x01) {\r
- if (PrivateData->Pmem64Base > Base) {\r
- PrivateData->Pmem64Base = Base;\r
- }\r
- if (PrivateData->Pmem64Limit < Limit) {\r
- PrivateData->Pmem64Limit = Limit;\r
- }\r
- }\r
- }\r
-\r
- //\r
- // Look at the PPB Configuration for legacy decoding attributes\r
- //\r
- if (PciConfigurationHeader.Bridge.BridgeControl & 0x04) {\r
- PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;\r
- PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;\r
- }\r
- if (PciConfigurationHeader.Bridge.BridgeControl & 0x08) {\r
- PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
- PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;\r
- PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;\r
- }\r
-\r
- } else {\r
- //\r
- // Parse the BARs of the PCI device to determine what I/O Ranges,\r
- // Memory Ranges, and Prefetchable Memory Ranges the device is decoding\r
- //\r
- if ((PciConfigurationHeader.Hdr.HeaderType & HEADER_LAYOUT_CODE) == HEADER_TYPE_DEVICE) {\r
- Status = PcatPciRootBridgeParseBars (\r
- PrivateData, \r
- PciConfigurationHeader.Hdr.Command,\r
- PrimaryBusIndex, \r
- Device, \r
- Function\r
- );\r
- }\r
-\r
- //\r
- // See if the PCI device is an IDE controller\r
- //\r
- if (PciConfigurationHeader.Hdr.ClassCode[2] == 0x01 &&\r
- PciConfigurationHeader.Hdr.ClassCode[1] == 0x01 ) {\r
- if (PciConfigurationHeader.Hdr.ClassCode[0] & 0x80) {\r
- PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;\r
- PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;\r
- }\r
- if (PciConfigurationHeader.Hdr.ClassCode[0] & 0x01) {\r
- PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;\r
- }\r
- if (PciConfigurationHeader.Hdr.ClassCode[0] & 0x04) {\r
- PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;\r
- }\r
- }\r
-\r
- //\r
- // See if the PCI device is a legacy VGA controller\r
- //\r
- if (PciConfigurationHeader.Hdr.ClassCode[2] == 0x00 &&\r
- PciConfigurationHeader.Hdr.ClassCode[1] == 0x01 ) {\r
- PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
- PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;\r
- PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;\r
- }\r
-\r
- //\r
- // See if the PCI device is a standard VGA controller\r
- //\r
- if (PciConfigurationHeader.Hdr.ClassCode[2] == 0x03 &&\r
- PciConfigurationHeader.Hdr.ClassCode[1] == 0x00 ) {\r
- PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
- PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;\r
- PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;\r
- }\r
-\r
- //\r
- // See if the PCI Device is a PCI - ISA or PCI - EISA \r
- // or ISA_POSITIVIE_DECODE Bridge device\r
- //\r
- if (PciConfigurationHeader.Hdr.ClassCode[2] == 0x06) {\r
- if (PciConfigurationHeader.Hdr.ClassCode[1] == 0x01 ||\r
- PciConfigurationHeader.Hdr.ClassCode[1] == 0x02 || \r
- PciConfigurationHeader.Hdr.ClassCode[1] == 0x80 ) {\r
- PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;\r
- PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;\r
-\r
- if (PrivateData->MemBase > 0xa0000) {\r
- PrivateData->MemBase = 0xa0000;\r
- }\r
- if (PrivateData->MemLimit < 0xbffff) {\r
- PrivateData->MemLimit = 0xbffff;\r
- }\r
- }\r
- }\r
- }\r
-\r
- //\r
- // If this device is not a multi function device, then skip the rest of this PCI device\r
- //\r
- if (Function == 0 && !(PciConfigurationHeader.Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)) {\r
- break;\r
- }\r
- }\r
- }\r
-\r
- //\r
- // After scanning all the PCI devices on the PCI root bridge's primary bus, update the \r
- // Primary Bus Number for the next PCI root bridge to be this PCI root bridge's subordinate\r
- // bus number + 1.\r
- //\r
- PrimaryBusIndex = PrivateData->SubordinateBus + 1;\r
-\r
- //\r
- // If at least one PCI device was found on the primary bus of this PCI root bridge, then the PCI root bridge\r
- // exists.\r
- //\r
- if (NumberOfPciDevices > 0) {\r
-\r
- //\r
- // Adjust the I/O range used for bounds checking for the legacy decoding attributed\r
- //\r
- if (PrivateData->Attributes & 0x7f) {\r
- PrivateData->IoBase = 0;\r
- if (PrivateData->IoLimit < 0xffff) {\r
- PrivateData->IoLimit = 0xffff;\r
- }\r
- }\r
-\r
- //\r
- // Adjust the Memory range used for bounds checking for the legacy decoding attributed\r
- //\r
- if (PrivateData->Attributes & EFI_PCI_ATTRIBUTE_VGA_MEMORY) {\r
- if (PrivateData->MemBase > 0xa0000) {\r
- PrivateData->MemBase = 0xa0000;\r
- }\r
- if (PrivateData->MemLimit < 0xbffff) {\r
- PrivateData->MemLimit = 0xbffff;\r
- }\r
- }\r
-\r
- //\r
- // Build ACPI descriptors for the resources on the PCI Root Bridge\r
- //\r
- Status = ConstructConfiguration(PrivateData);\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- //\r
- // Create the handle for this PCI Root Bridge \r
- //\r
- Status = gBS->InstallMultipleProtocolInterfaces (\r
- &PrivateData->Handle, \r
- &gEfiDevicePathProtocolGuid,\r
- PrivateData->DevicePath,\r
- &gEfiPciRootBridgeIoProtocolGuid,\r
- &PrivateData->Io,\r
- NULL\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- //\r
- // Contruct DeviceIoProtocol\r
- //\r
- Status = DeviceIoConstructor (\r
- PrivateData->Handle,\r
- &PrivateData->Io,\r
- PrivateData->DevicePath,\r
- (UINT16)PrivateData->PrimaryBus,\r
- (UINT16)PrivateData->SubordinateBus\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- //\r
- // Scan this PCI Root Bridge for PCI Option ROMs and add them to the PCI Option ROM Table\r
- //\r
- Status = ScanPciRootBridgeForRoms(&PrivateData->Io);\r
-\r
- //\r
- // Increment the index for the next PCI Root Bridge\r
- //\r
- PciRootBridgeIndex++;\r
-\r
- } else {\r
-\r
- //\r
- // If no PCI Root Bridges were found on the current PCI segment, then exit\r
- //\r
- if (NumberOfPciRootBridges == 0) {\r
- Status = EFI_SUCCESS;\r
- goto Done;\r
- }\r
-\r
- }\r
-\r
- //\r
- // If the PrimaryBusIndex is greater than the maximum allowable PCI bus number, then\r
- // the PCI Segment Number is incremented, and the next segment is searched starting at Bus #0\r
- // Otherwise, the search is continued on the next PCI Root Bridge\r
- //\r
- if (PrimaryBusIndex > PCI_MAX_BUS) {\r
- PciSegmentIndex++;\r
- NumberOfPciRootBridges = 0;\r
- PrimaryBusIndex = 0;\r
- } else {\r
- NumberOfPciRootBridges++;\r
- }\r
-\r
- }\r
-\r
- return EFI_SUCCESS;\r
-\r
-Done:\r
- //\r
- // Clean up memory allocated for the PCI Root Bridge that was searched but not created.\r
- //\r
- if (PrivateData) {\r
- if (PrivateData->DevicePath) {\r
- gBS->FreePool(PrivateData->DevicePath);\r
- }\r
- gBS->FreePool (PrivateData);\r
- }\r
-\r
- //\r
- // If no PCI Root Bridges were discovered, then return the error condition from scanning the\r
- // first PCI Root Bridge\r
- //\r
- if (PciRootBridgeIndex == 0) {\r
- return Status;\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-EFI_STATUS \r
-ConstructConfiguration(\r
- IN OUT PCAT_PCI_ROOT_BRIDGE_INSTANCE *PrivateData\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
- \r
-{\r
- EFI_STATUS Status;\r
- UINT8 NumConfig;\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;\r
- EFI_ACPI_END_TAG_DESCRIPTOR *ConfigurationEnd;\r
-\r
- NumConfig = 0;\r
- PrivateData->Configuration = NULL;\r
-\r
- if (PrivateData->SubordinateBus >= PrivateData->PrimaryBus) {\r
- NumConfig++;\r
- }\r
- if (PrivateData->IoLimit >= PrivateData->IoBase) {\r
- NumConfig++;\r
- }\r
- if (PrivateData->Mem32Limit >= PrivateData->Mem32Base) {\r
- NumConfig++;\r
- }\r
- if (PrivateData->Pmem32Limit >= PrivateData->Pmem32Base) {\r
- NumConfig++;\r
- }\r
- if (PrivateData->Mem64Limit >= PrivateData->Mem64Base) {\r
- NumConfig++;\r
- }\r
- if (PrivateData->Pmem64Limit >= PrivateData->Pmem64Base) {\r
- NumConfig++;\r
- }\r
-\r
- if ( NumConfig == 0 ) {\r
-\r
- //\r
- // If there is no resource request\r
- //\r
- Status = gBS->AllocatePool (\r
- EfiBootServicesData, \r
- sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR),\r
- (VOID **)&PrivateData->Configuration\r
- );\r
- if (EFI_ERROR (Status )) {\r
- return Status;\r
- }\r
-\r
- Configuration = PrivateData->Configuration;\r
- \r
- ZeroMem (\r
- Configuration, \r
- sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR) \r
- );\r
- \r
- Configuration->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
- Configuration->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
- Configuration++;\r
-\r
- ConfigurationEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *)(Configuration);\r
- ConfigurationEnd->Desc = ACPI_END_TAG_DESCRIPTOR;\r
- ConfigurationEnd->Checksum = 0;\r
- }\r
-\r
- //\r
- // If there is at least one type of resource request,\r
- // allocate a acpi resource node \r
- //\r
- Status = gBS->AllocatePool (\r
- EfiBootServicesData, \r
- sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR),\r
- (VOID **)&PrivateData->Configuration\r
- );\r
- if (EFI_ERROR (Status )) {\r
- return Status;\r
- }\r
- \r
- Configuration = PrivateData->Configuration;\r
-\r
- ZeroMem (\r
- Configuration, \r
- sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)\r
- );\r
-\r
- if (PrivateData->SubordinateBus >= PrivateData->PrimaryBus) {\r
- Configuration->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
- Configuration->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
- Configuration->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS;\r
- Configuration->SpecificFlag = 0; \r
- Configuration->AddrRangeMin = PrivateData->PrimaryBus;\r
- Configuration->AddrRangeMax = PrivateData->SubordinateBus;\r
- Configuration->AddrLen = Configuration->AddrRangeMax - Configuration->AddrRangeMin + 1;\r
- Configuration++;\r
- }\r
- //\r
- // Deal with io aperture\r
- //\r
- if (PrivateData->IoLimit >= PrivateData->IoBase) {\r
- Configuration->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
- Configuration->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
- Configuration->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;\r
- Configuration->SpecificFlag = 1; //non ISA range\r
- Configuration->AddrRangeMin = PrivateData->IoBase;\r
- Configuration->AddrRangeMax = PrivateData->IoLimit;\r
- Configuration->AddrLen = Configuration->AddrRangeMax - Configuration->AddrRangeMin + 1;\r
- Configuration++;\r
- }\r
-\r
- //\r
- // Deal with mem32 aperture\r
- //\r
- if (PrivateData->Mem32Limit >= PrivateData->Mem32Base) {\r
- Configuration->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
- Configuration->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
- Configuration->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
- Configuration->SpecificFlag = 0; //Nonprefechable\r
- Configuration->AddrSpaceGranularity = 32; //32 bit\r
- Configuration->AddrRangeMin = PrivateData->Mem32Base;\r
- Configuration->AddrRangeMax = PrivateData->Mem32Limit;\r
- Configuration->AddrLen = Configuration->AddrRangeMax - Configuration->AddrRangeMin + 1;\r
- Configuration++;\r
- } \r
-\r
- //\r
- // Deal with Pmem32 aperture\r
- //\r
- if (PrivateData->Pmem32Limit >= PrivateData->Pmem32Base) {\r
- Configuration->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
- Configuration->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
- Configuration->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
- Configuration->SpecificFlag = 0x6; //prefechable\r
- Configuration->AddrSpaceGranularity = 32; //32 bit\r
- Configuration->AddrRangeMin = PrivateData->Pmem32Base;\r
- Configuration->AddrRangeMax = PrivateData->Pmem32Limit;\r
- Configuration->AddrLen = Configuration->AddrRangeMax - Configuration->AddrRangeMin + 1;\r
- Configuration++;\r
- }\r
-\r
- //\r
- // Deal with mem64 aperture\r
- //\r
- if (PrivateData->Mem64Limit >= PrivateData->Mem64Base) {\r
- Configuration->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
- Configuration->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
- Configuration->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
- Configuration->SpecificFlag = 0; //nonprefechable\r
- Configuration->AddrSpaceGranularity = 64; //32 bit\r
- Configuration->AddrRangeMin = PrivateData->Mem64Base;\r
- Configuration->AddrRangeMax = PrivateData->Mem64Limit;\r
- Configuration->AddrLen = Configuration->AddrRangeMax - Configuration->AddrRangeMin + 1;\r
- Configuration++;\r
- }\r
-\r
- //\r
- // Deal with Pmem64 aperture\r
- //\r
- if (PrivateData->Pmem64Limit >= PrivateData->Pmem64Base) {\r
- Configuration->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
- Configuration->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
- Configuration->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
- Configuration->SpecificFlag = 0x06; //prefechable\r
- Configuration->AddrSpaceGranularity = 64; //32 bit\r
- Configuration->AddrRangeMin = PrivateData->Pmem64Base;\r
- Configuration->AddrRangeMax = PrivateData->Pmem64Limit;\r
- Configuration->AddrLen = Configuration->AddrRangeMax - Configuration->AddrRangeMin + 1;\r
- Configuration++;\r
- }\r
-\r
- //\r
- // put the checksum\r
- //\r
- ConfigurationEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *)(Configuration);\r
- ConfigurationEnd->Desc = ACPI_END_TAG_DESCRIPTOR;\r
- ConfigurationEnd->Checksum = 0;\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-EFI_STATUS \r
-PcatPciRootBridgeBarExisted (\r
- IN PCAT_PCI_ROOT_BRIDGE_INSTANCE *PrivateData,\r
- IN UINT64 Address,\r
- OUT UINT32 *OriginalValue,\r
- OUT UINT32 *Value\r
- ) \r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-{\r
- EFI_STATUS Status;\r
- UINT32 AllOnes;\r
- EFI_TPL OldTpl;\r
-\r
- //\r
- // Preserve the original value\r
- //\r
- Status = PrivateData->Io.Pci.Read (\r
- &PrivateData->Io, \r
- EfiPciWidthUint32, \r
- Address, \r
- 1, \r
- OriginalValue\r
- );\r
-\r
- //\r
- // Raise TPL to high level to disable timer interrupt while the BAR is probed\r
- //\r
- OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);\r
-\r
- AllOnes = 0xffffffff;\r
-\r
- Status = PrivateData->Io.Pci.Write (\r
- &PrivateData->Io, \r
- EfiPciWidthUint32, \r
- Address, \r
- 1, \r
- &AllOnes\r
- );\r
- Status = PrivateData->Io.Pci.Read (\r
- &PrivateData->Io, \r
- EfiPciWidthUint32, \r
- Address, \r
- 1, \r
- Value\r
- );\r
-\r
- //\r
- //Write back the original value\r
- //\r
- Status = PrivateData->Io.Pci.Write (\r
- &PrivateData->Io, \r
- EfiPciWidthUint32, \r
- Address, \r
- 1, \r
- OriginalValue\r
- );\r
-\r
- //\r
- // Restore TPL to its original level\r
- //\r
- gBS->RestoreTPL (OldTpl);\r
-\r
- if ( *Value == 0 ) {\r
- return EFI_DEVICE_ERROR;\r
- }\r
- return Status;\r
-}\r
-\r
-EFI_STATUS\r
-PcatPciRootBridgeParseBars (\r
- IN PCAT_PCI_ROOT_BRIDGE_INSTANCE *PrivateData,\r
- IN UINT16 Command,\r
- IN UINTN Bus,\r
- IN UINTN Device,\r
- IN UINTN Function\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-{\r
- EFI_STATUS Status;\r
- UINT64 Address;\r
- UINT32 OriginalValue;\r
- UINT32 Value;\r
- UINT32 OriginalUpperValue;\r
- UINT32 UpperValue;\r
- UINT64 Mask;\r
- UINTN Offset;\r
- UINT64 Base;\r
- UINT64 Length;\r
- UINT64 Limit;\r
-\r
- for (Offset = 0x10; Offset < 0x28; Offset += 4) {\r
- Address = EFI_PCI_ADDRESS (Bus, Device, Function, Offset);\r
- Status = PcatPciRootBridgeBarExisted (\r
- PrivateData,\r
- Address,\r
- &OriginalValue,\r
- &Value\r
- );\r
-\r
- if (!EFI_ERROR (Status )) {\r
- if ( Value & 0x01 ) { \r
- if (Command & 0x0001) {\r
- //\r
- //Device I/Os\r
- //\r
- Mask = 0xfffffffc;\r
- Base = OriginalValue & Mask;\r
- Length = ((~(Value & Mask)) & Mask) + 0x04;\r
- if (!(Value & 0xFFFF0000)){\r
- Length &= 0x0000FFFF;\r
- }\r
- Limit = Base + Length - 1;\r
-\r
- if (Base < Limit) {\r
- if (PrivateData->IoBase > Base) {\r
- PrivateData->IoBase = (UINT32)Base;\r
- }\r
- if (PrivateData->IoLimit < Limit) {\r
- PrivateData->IoLimit = (UINT32)Limit;\r
- }\r
- }\r
- }\r
- \r
- } else {\r
-\r
- if (Command & 0x0002) {\r
-\r
- Mask = 0xfffffff0;\r
- Base = OriginalValue & Mask;\r
- Length = Value & Mask;\r
- \r
- if ((Value & 0x07) != 0x04) {\r
- Length = ((~Length) + 1) & 0xffffffff;\r
- } else {\r
- Offset += 4; \r
- Address = EFI_PCI_ADDRESS (Bus, Device, Function, Offset);\r
-\r
- Status = PcatPciRootBridgeBarExisted (\r
- PrivateData,\r
- Address,\r
- &OriginalUpperValue,\r
- &UpperValue\r
- );\r
-\r
- Base = Base | LShiftU64((UINT64)OriginalUpperValue,32);\r
- Length = Length | LShiftU64((UINT64)UpperValue,32);\r
- Length = (~Length) + 1;\r
- }\r
-\r
- Limit = Base + Length - 1;\r
-\r
- if (Base < Limit) {\r
- if (PrivateData->MemBase > Base) {\r
- PrivateData->MemBase = Base;\r
- }\r
- if (PrivateData->MemLimit < Limit) {\r
- PrivateData->MemLimit = Limit;\r
- }\r
-\r
- switch (Value &0x07) {\r
- case 0x00: ////memory space; anywhere in 32 bit address space\r
- if (Value & 0x08) {\r
- if (PrivateData->Pmem32Base > Base) {\r
- PrivateData->Pmem32Base = Base;\r
- }\r
- if (PrivateData->Pmem32Limit < Limit) {\r
- PrivateData->Pmem32Limit = Limit;\r
- }\r
- } else {\r
- if (PrivateData->Mem32Base > Base) {\r
- PrivateData->Mem32Base = Base;\r
- }\r
- if (PrivateData->Mem32Limit < Limit) {\r
- PrivateData->Mem32Limit = Limit;\r
- }\r
- }\r
- break;\r
- case 0x04: //memory space; anywhere in 64 bit address space\r
- if (Value & 0x08) {\r
- if (PrivateData->Pmem64Base > Base) {\r
- PrivateData->Pmem64Base = Base;\r
- }\r
- if (PrivateData->Pmem64Limit < Limit) {\r
- PrivateData->Pmem64Limit = Limit;\r
- }\r
- } else {\r
- if (PrivateData->Mem64Base > Base) {\r
- PrivateData->Mem64Base = Base;\r
- }\r
- if (PrivateData->Mem64Limit < Limit) {\r
- PrivateData->Mem64Limit = Limit;\r
- }\r
- }\r
- break;\r
- }\r
- }\r
- }\r
- }\r
- }\r
- }\r
- return EFI_SUCCESS;\r
-}\r
-\r
-UINT64\r
-GetPciExpressBaseAddressForRootBridge (\r
- IN UINTN HostBridgeNumber,\r
- IN UINTN RootBridgeNumber\r
- )\r
-/*++\r
-\r
-Routine Description:\r
- This routine is to get PciExpress Base Address for this RootBridge\r
-\r
-Arguments:\r
- HostBridgeNumber - The number of HostBridge\r
- RootBridgeNumber - The number of RootBridge\r
- \r
-Returns:\r
- UINT64 - PciExpressBaseAddress for this HostBridge and RootBridge\r
-\r
---*/\r
-{\r
- EFI_PCI_EXPRESS_BASE_ADDRESS_INFORMATION *PciExpressBaseAddressInfo;\r
- UINTN BufferSize;\r
- UINT32 Index;\r
- UINT32 Number;\r
- EFI_PEI_HOB_POINTERS GuidHob;\r
-\r
- //\r
- // Get PciExpressAddressInfo Hob\r
- //\r
- PciExpressBaseAddressInfo = NULL;\r
- BufferSize = 0;\r
- GuidHob.Raw = GetFirstGuidHob (&gEfiPciExpressBaseAddressGuid);\r
- if (GuidHob.Raw != NULL) {\r
- PciExpressBaseAddressInfo = GET_GUID_HOB_DATA (GuidHob.Guid);\r
- BufferSize = GET_GUID_HOB_DATA_SIZE (GuidHob.Guid);\r
- } else {\r
- return 0;\r
- }\r
-\r
- //\r
- // Search the PciExpress Base Address in the Hob for current RootBridge\r
- //\r
- Number = (UINT32)(BufferSize / sizeof(EFI_PCI_EXPRESS_BASE_ADDRESS_INFORMATION));\r
- for (Index = 0; Index < Number; Index++) {\r
- if ((PciExpressBaseAddressInfo[Index].HostBridgeNumber == HostBridgeNumber) &&\r
- (PciExpressBaseAddressInfo[Index].RootBridgeNumber == RootBridgeNumber)) {\r
- return PciExpressBaseAddressInfo[Index].PciExpressBaseAddress;\r
- }\r
- }\r
-\r
- //\r
- // Do not find the PciExpress Base Address in the Hob\r
- //\r
- return 0;\r
-}\r
-\r
projects / mirror_edk2.git / blobdiff