Update the copyright notice format

[mirror_edk2.git] / DuetPkg / PciRootBridgeNoEnumerationDxe / X64 / PcatIo.c

diff --git a/DuetPkg/PciRootBridgeNoEnumerationDxe/X64/PcatIo.c b/DuetPkg/PciRootBridgeNoEnumerationDxe/X64/PcatIo.c
index 0a786f823d7ef4a6f80118c0122e2d030f7a8ff1..56da796a4339b7f7f12ce82e6559d49b228ab78c 100644 (file)
--- a/DuetPkg/PciRootBridgeNoEnumerationDxe/X64/PcatIo.c
+++ b/DuetPkg/PciRootBridgeNoEnumerationDxe/X64/PcatIo.c
@@ -1,7 +1,7 @@
 /*++\r
 \r
-Copyright (c) 2005 - 2006, Intel Corporation                                                         \r
-All rights reserved. This program and the accompanying materials                          \r
+Copyright (c) 2005 - 2006, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials                          \r
 are licensed and made available under the terms and conditions of the BSD License         \r
 which accompanies this distribution.  The full text of the license may be found at        \r
 http://opensource.org/licenses/bsd-license.php                                            \r
@@ -22,8 +22,8 @@ Revision History
 \r
 #include "PcatPciRootBridge.h"\r
 \r
-static BOOLEAN                  mPciOptionRomTableInstalled = FALSE;\r
-static EFI_PCI_OPTION_ROM_TABLE mPciOptionRomTable          = {0, NULL};\r
+BOOLEAN                  mPciOptionRomTableInstalled = FALSE;\r
+EFI_PCI_OPTION_ROM_TABLE mPciOptionRomTable          = {0, NULL};\r
 \r
 EFI_STATUS\r
 PcatRootBridgeIoIoRead (\r
@@ -129,7 +129,7 @@ PcatRootBridgeIoPciRW (
     // Check PciExpressBaseAddress\r
     //\r
     if ((PrivateData->PciExpressBaseAddress == 0) ||\r
-        (PrivateData->PciExpressBaseAddress >= EFI_MAX_ADDRESS)) {\r
+        (PrivateData->PciExpressBaseAddress >= MAX_ADDRESS)) {\r
       return EFI_UNSUPPORTED;\r
     } else {\r
       UsePciExpressAccess = TRUE;\r
@@ -208,7 +208,6 @@ PcatRootBridgeIoPciRW (
   return EFI_SUCCESS;\r
 }\r
 \r
-static\r
 VOID\r
 ScanPciBus(\r
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *IoDev,\r
@@ -297,7 +296,6 @@ ScanPciBus(
   }\r
 }\r
 \r
-static\r
 VOID\r
 CheckForRom (\r
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *IoDev,\r
@@ -477,7 +475,7 @@ CheckForRom (
             Status = gBS->AllocatePool(\r
                             EfiBootServicesData,\r
                             ((UINT32)mPciOptionRomTable.PciOptionRomCount + 1) * sizeof(EFI_PCI_OPTION_ROM_DESCRIPTOR),\r
-                            &TempPciOptionRomDescriptors\r
+                            (VOID **) &TempPciOptionRomDescriptors\r
                             );\r
             if (mPciOptionRomTable.PciOptionRomCount > 0) {\r
               CopyMem(\r
@@ -523,7 +521,6 @@ CheckForRom (
   IoDev->Pci.Write (IoDev, EfiPciWidthUint32, Address, sizeof(PciHeader)/sizeof(UINT32), &PciHeader);\r
 }\r
 \r
-static\r
 VOID\r
 SaveCommandRegister (\r
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *IoDev,\r
@@ -556,12 +553,11 @@ SaveCommandRegister (
   //\r
   // Clear the memory enable bit\r
   //\r
-  Command = Context->CommandRegisterBuffer[Index] & (~0x02);\r
+  Command = (UINT16) (Context->CommandRegisterBuffer[Index] & (~0x02));\r
 \r
   IoDev->Pci.Write (IoDev, EfiPciWidthUint16, Address, 1, &Command);\r
 }\r
 \r
-static\r
 VOID\r
 RestoreCommandRegister (\r
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *IoDev,\r
@@ -610,7 +606,7 @@ ScanPciRootBridgeForRoms(
     mPciOptionRomTableInstalled = TRUE;\r
   }\r
 \r
-  Status = IoDev->Configuration(IoDev, &Descriptors);\r
+  Status = IoDev->Configuration(IoDev, (VOID **) &Descriptors);\r
   if (EFI_ERROR (Status) || Descriptors == NULL) {\r
     return EFI_NOT_FOUND;\r
   }\r
@@ -634,7 +630,7 @@ ScanPciRootBridgeForRoms(
       //\r
       // Find Memory Descriptors that are less than 4GB, so the PPB Memory Window can be used for downstream devices\r
       //\r
-      if (Descriptors->AddrRangeMax < 0x100000000) {\r
+      if (Descriptors->AddrRangeMax < 0x100000000ULL) {\r
         //\r
         // Find the largest Non-Prefetchable Memory Descriptor that is less than 4GB\r
         //\r
@@ -681,7 +677,7 @@ ScanPciRootBridgeForRoms(
   Status = gBS->AllocatePool(\r
                   EfiBootServicesData,\r
                   sizeof(UINT16) * (MaxBus - MinBus + 1) * (PCI_MAX_DEVICE+1) * (PCI_MAX_FUNC+1),\r
-                  &Context.CommandRegisterBuffer\r
+                  (VOID **) &Context.CommandRegisterBuffer\r
                   );\r
 \r
   if (EFI_ERROR (Status)) {\r