in the ARM Namespace\r
*/\r
typedef enum ArmObjectID {\r
- EArmObjReserved, ///< 0 - Reserved\r
- EArmObjBootArchInfo, ///< 1 - Boot Architecture Info\r
- EArmObjCpuInfo, ///< 2 - CPU Info\r
- EArmObjPowerManagementProfileInfo, ///< 3 - Power Management Profile Info\r
- EArmObjGicCInfo, ///< 4 - GIC CPU Interface Info\r
- EArmObjGicDInfo, ///< 5 - GIC Distributor Info\r
- EArmObjGicMsiFrameInfo, ///< 6 - GIC MSI Frame Info\r
- EArmObjGicRedistributorInfo, ///< 7 - GIC Redistributor Info\r
- EArmObjGicItsInfo, ///< 8 - GIC ITS Info\r
- EArmObjSerialConsolePortInfo, ///< 9 - Serial Console Port Info\r
- EArmObjSerialDebugPortInfo, ///< 10 - Serial Debug Port Info\r
- EArmObjGenericTimerInfo, ///< 11 - Generic Timer Info\r
- EArmObjPlatformGTBlockInfo, ///< 12 - Platform GT Block Info\r
- EArmObjGTBlockTimerFrameInfo, ///< 13 - Generic Timer Block Frame Info\r
- EArmObjPlatformGenericWatchdogInfo, ///< 14 - Platform Generic Watchdog\r
- EArmObjPciConfigSpaceInfo, ///< 15 - PCI Configuration Space Info\r
- EArmObjHypervisorVendorIdentity, ///< 16 - Hypervisor Vendor Id\r
- EArmObjFixedFeatureFlags, ///< 17 - Fixed feature flags for FADT\r
- EArmObjItsGroup, ///< 18 - ITS Group\r
- EArmObjNamedComponent, ///< 19 - Named Component\r
- EArmObjRootComplex, ///< 20 - Root Complex\r
- EArmObjSmmuV1SmmuV2, ///< 21 - SMMUv1 or SMMUv2\r
- EArmObjSmmuV3, ///< 22 - SMMUv3\r
- EArmObjPmcg, ///< 23 - PMCG\r
- EArmObjGicItsIdentifierArray, ///< 24 - GIC ITS Identifier Array\r
- EArmObjIdMappingArray, ///< 25 - ID Mapping Array\r
- EArmObjSmmuInterruptArray, ///< 26 - SMMU Interrupt Array\r
- EArmObjProcHierarchyInfo, ///< 27 - Processor Hierarchy Info\r
- EArmObjCacheInfo, ///< 28 - Cache Info\r
- EArmObjProcNodeIdInfo, ///< 29 - Processor Hierarchy Node ID Info\r
- EArmObjCmRef, ///< 30 - CM Object Reference\r
+ EArmObjReserved, ///< 0 - Reserved\r
+ EArmObjBootArchInfo, ///< 1 - Boot Architecture Info\r
+ EArmObjCpuInfo, ///< 2 - CPU Info\r
+ EArmObjPowerManagementProfileInfo, ///< 3 - Power Management Profile Info\r
+ EArmObjGicCInfo, ///< 4 - GIC CPU Interface Info\r
+ EArmObjGicDInfo, ///< 5 - GIC Distributor Info\r
+ EArmObjGicMsiFrameInfo, ///< 6 - GIC MSI Frame Info\r
+ EArmObjGicRedistributorInfo, ///< 7 - GIC Redistributor Info\r
+ EArmObjGicItsInfo, ///< 8 - GIC ITS Info\r
+ EArmObjSerialConsolePortInfo, ///< 9 - Serial Console Port Info\r
+ EArmObjSerialDebugPortInfo, ///< 10 - Serial Debug Port Info\r
+ EArmObjGenericTimerInfo, ///< 11 - Generic Timer Info\r
+ EArmObjPlatformGTBlockInfo, ///< 12 - Platform GT Block Info\r
+ EArmObjGTBlockTimerFrameInfo, ///< 13 - Generic Timer Block Frame Info\r
+ EArmObjPlatformGenericWatchdogInfo, ///< 14 - Platform Generic Watchdog\r
+ EArmObjPciConfigSpaceInfo, ///< 15 - PCI Configuration Space Info\r
+ EArmObjHypervisorVendorIdentity, ///< 16 - Hypervisor Vendor Id\r
+ EArmObjFixedFeatureFlags, ///< 17 - Fixed feature flags for FADT\r
+ EArmObjItsGroup, ///< 18 - ITS Group\r
+ EArmObjNamedComponent, ///< 19 - Named Component\r
+ EArmObjRootComplex, ///< 20 - Root Complex\r
+ EArmObjSmmuV1SmmuV2, ///< 21 - SMMUv1 or SMMUv2\r
+ EArmObjSmmuV3, ///< 22 - SMMUv3\r
+ EArmObjPmcg, ///< 23 - PMCG\r
+ EArmObjGicItsIdentifierArray, ///< 24 - GIC ITS Identifier Array\r
+ EArmObjIdMappingArray, ///< 25 - ID Mapping Array\r
+ EArmObjSmmuInterruptArray, ///< 26 - SMMU Interrupt Array\r
+ EArmObjProcHierarchyInfo, ///< 27 - Processor Hierarchy Info\r
+ EArmObjCacheInfo, ///< 28 - Cache Info\r
+ EArmObjProcNodeIdInfo, ///< 29 - Processor Node ID Info\r
+ EArmObjCmRef, ///< 30 - CM Object Reference\r
+ EArmObjMemoryAffinityInfo, ///< 31 - Memory Affinity Info\r
+ EArmObjDeviceHandleAcpi, ///< 32 - Device Handle Acpi\r
+ EArmObjDeviceHandlePci, ///< 33 - Device Handle Pci\r
+ EArmObjGenericInitiatorAffinityInfo, ///< 34 - Generic Initiator Affinity\r
EArmObjMax\r
} EARM_OBJECT_ID;\r
\r
generating MADT revision 4 or lower.\r
*/\r
UINT16 SpeOverflowInterrupt;\r
+\r
+ /** The proximity domain to which the logical processor belongs.\r
+ This field is used to populate the GICC affinity structure\r
+ in the SRAT table.\r
+ */\r
+ UINT32 ProximityDomain;\r
+\r
+ /** The clock domain to which the logical processor belongs.\r
+ This field is used to populate the GICC affinity structure\r
+ in the SRAT table.\r
+ */\r
+ UINT32 ClockDomain;\r
+\r
+ /** The GICC Affinity flags field as described by the GICC Affinity structure\r
+ in the SRAT table.\r
+ */\r
+ UINT32 AffinityFlags;\r
} CM_ARM_GICC_INFO;\r
\r
/** A structure that describes the\r
\r
/// The physical address for the Interrupt Translation Service\r
UINT64 PhysicalBaseAddress;\r
+\r
+ /** The proximity domain to which the logical processor belongs.\r
+ This field is used to populate the GIC ITS affinity structure\r
+ in the SRAT table.\r
+ */\r
+ UINT32 ProximityDomain;\r
} CM_ARM_GIC_ITS_INFO;\r
\r
/** A structure that describes the\r
CM_OBJECT_TOKEN ReferenceToken;\r
} CM_ARM_OBJ_REF;\r
\r
+/** A structure that describes the Memory Affinity Structure (Type 1) in SRAT\r
+\r
+ ID: EArmObjMemoryAffinityInfo\r
+*/\r
+typedef struct CmArmMemoryAffinityInfo {\r
+ /// The proximity domain to which the "range of memory" belongs.\r
+ UINT32 ProximityDomain;\r
+\r
+ /// Base Address\r
+ UINT64 BaseAddress;\r
+\r
+ /// Length\r
+ UINT64 Length;\r
+\r
+ /// Flags\r
+ UINT32 Flags;\r
+} CM_ARM_MEMORY_AFFINITY_INFO;\r
+\r
+/** A structure that describes the ACPI Device Handle (Type 0) in the\r
+ Generic Initiator Affinity structure in SRAT\r
+\r
+ ID: EArmObjDeviceHandleAcpi\r
+*/\r
+typedef struct CmArmDeviceHandleAcpi {\r
+ /// Hardware ID\r
+ UINT64 Hid;\r
+\r
+ /// Unique Id\r
+ UINT32 Uid;\r
+} CM_ARM_DEVICE_HANDLE_ACPI;\r
+\r
+/** A structure that describes the PCI Device Handle (Type 1) in the\r
+ Generic Initiator Affinity structure in SRAT\r
+\r
+ ID: EArmObjDeviceHandlePci\r
+*/\r
+typedef struct CmArmDeviceHandlePci {\r
+ /// PCI Segment Number\r
+ UINT16 SegmentNumber;\r
+\r
+ /// PCI Bus Number - Max 256 busses (Bits 15:8 of BDF)\r
+ UINT8 BusNumber;\r
+\r
+ /// PCI Device Mumber - Max 32 devices (Bits 7:3 of BDF)\r
+ UINT8 DeviceNumber;\r
+\r
+ /// PCI Function Number - Max 8 functions (Bits 2:0 of BDF)\r
+ UINT8 FunctionNumber;\r
+} CM_ARM_DEVICE_HANDLE_PCI;\r
+\r
+/** A structure that describes the Generic Initiator Affinity structure in SRAT\r
+\r
+ ID: EArmObjGenericInitiatorAffinityInfo\r
+*/\r
+typedef struct CmArmGenericInitiatorAffinityInfo {\r
+ /// The proximity domain to which the generic initiator belongs.\r
+ UINT32 ProximityDomain;\r
+\r
+ /// Flags\r
+ UINT32 Flags;\r
+\r
+ /// Device Handle Type\r
+ UINT8 DeviceHandleType;\r
+\r
+ /// Reference Token for the Device Handle\r
+ CM_OBJECT_TOKEN DeviceHandleToken;\r
+} CM_ARM_GENERIC_INITIATOR_AFFINITY_INFO;\r
+\r
#pragma pack()\r
\r
#endif // ARM_NAMESPACE_OBJECTS_H_\r
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