+++ /dev/null
-/*++\r
-\r
-Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-\r
-Module Name:\r
-\r
- CpuIA32.h\r
-\r
-Abstract:\r
-\r
---*/\r
-\r
-#ifndef _CPU_IA32_H\r
-#define _CPU_IA32_H\r
-\r
-#include "Tiano.h"\r
-\r
-typedef struct {\r
- UINT32 RegEax;\r
- UINT32 RegEbx;\r
- UINT32 RegEcx;\r
- UINT32 RegEdx;\r
-} EFI_CPUID_REGISTER;\r
-\r
-typedef struct {\r
- UINT32 HeaderVersion;\r
- UINT32 UpdateRevision;\r
- UINT32 Date;\r
- UINT32 ProcessorId;\r
- UINT32 Checksum;\r
- UINT32 LoaderRevision;\r
- UINT32 ProcessorFlags;\r
- UINT32 DataSize;\r
- UINT32 TotalSize;\r
- UINT8 Reserved[12];\r
-} EFI_CPU_MICROCODE_HEADER;\r
-\r
-typedef struct {\r
- UINT32 ExtendedSignatureCount;\r
- UINT32 ExtendedTableChecksum; \r
- UINT8 Reserved[12];\r
-} EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER;\r
-\r
-typedef struct {\r
- UINT32 ProcessorSignature;\r
- UINT32 ProcessorFlag;\r
- UINT32 ProcessorChecksum;\r
-} EFI_CPU_MICROCODE_EXTENDED_TABLE;\r
-\r
-typedef struct {\r
- UINT32 Stepping : 4;\r
- UINT32 Model : 4;\r
- UINT32 Family : 4;\r
- UINT32 Type : 2;\r
- UINT32 Reserved1 : 2;\r
- UINT32 ExtendedModel : 4;\r
- UINT32 ExtendedFamily : 8;\r
- UINT32 Reserved2 : 4;\r
-} EFI_CPU_VERSION;\r
-\r
-#define EFI_CPUID_SIGNATURE 0x0\r
-#define EFI_CPUID_VERSION_INFO 0x1\r
-#define EFI_CPUID_CACHE_INFO 0x2\r
-#define EFI_CPUID_SERIAL_NUMBER 0x3\r
-#define EFI_CPUID_EXTENDED_FUNCTION 0x80000000\r
-#define EFI_CPUID_EXTENDED_CPU_SIG 0x80000001\r
-#define EFI_CPUID_BRAND_STRING1 0x80000002\r
-#define EFI_CPUID_BRAND_STRING2 0x80000003\r
-#define EFI_CPUID_BRAND_STRING3 0x80000004\r
-\r
-#define EFI_MSR_IA32_PLATFORM_ID 0x17\r
-#define EFI_MSR_IA32_APIC_BASE 0x1B\r
-#define EFI_MSR_EBC_HARD_POWERON 0x2A\r
-#define EFI_MSR_EBC_SOFT_POWERON 0x2B\r
-#define BINIT_DRIVER_DISABLE 0x40\r
-#define INTERNAL_MCERR_DISABLE 0x20\r
-#define INITIATOR_MCERR_DISABLE 0x10\r
-#define EFI_MSR_EBC_FREQUENCY_ID 0x2C\r
-#define EFI_MSR_IA32_BIOS_UPDT_TRIG 0x79\r
-#define EFI_MSR_IA32_BIOS_SIGN_ID 0x8B\r
-#define EFI_MSR_PSB_CLOCK_STATUS 0xCD\r
-#define EFI_APIC_GLOBAL_ENABLE 0x800\r
-#define EFI_MSR_IA32_MISC_ENABLE 0x1A0\r
-#define LIMIT_CPUID_MAXVAL_ENABLE_BIT 0x00400000\r
-#define AUTOMATIC_THERMAL_CONTROL_ENABLE_BIT 0x00000008\r
-#define COMPATIBLE_FPU_OPCODE_ENABLE_BIT 0x00000004\r
-#define LOGICAL_PROCESSOR_PRIORITY_ENABLE_BIT 0x00000002\r
-#define FAST_STRING_ENABLE_BIT 0x00000001\r
-\r
-#define EFI_CACHE_VARIABLE_MTRR_BASE 0x200\r
-#define EFI_CACHE_VARIABLE_MTRR_END 0x20F\r
-#define EFI_CACHE_IA32_MTRR_DEF_TYPE 0x2FF\r
-#define EFI_CACHE_MTRR_VALID 0x800\r
-#define EFI_CACHE_FIXED_MTRR_VALID 0x400\r
-#define EFI_CACHE_VALID_ADDRESS 0xFFFFFF000\r
-#define EFI_MSR_VALID_MASK 0xFFFFFFFFF\r
-#define EFI_CACHE_VALID_EXTENDED_ADDRESS 0xFFFFFFFFFF000\r
-#define EFI_MSR_VALID_EXTENDED_MASK 0xFFFFFFFFFFFFF\r
-\r
-#define EFI_IA32_MTRR_FIX64K_00000 0x250\r
-#define EFI_IA32_MTRR_FIX16K_80000 0x258\r
-#define EFI_IA32_MTRR_FIX16K_A0000 0x259\r
-#define EFI_IA32_MTRR_FIX4K_C0000 0x268\r
-#define EFI_IA32_MTRR_FIX4K_C8000 0x269\r
-#define EFI_IA32_MTRR_FIX4K_D0000 0x26A\r
-#define EFI_IA32_MTRR_FIX4K_D8000 0x26B\r
-#define EFI_IA32_MTRR_FIX4K_E0000 0x26C\r
-#define EFI_IA32_MTRR_FIX4K_E8000 0x26D\r
-#define EFI_IA32_MTRR_FIX4K_F0000 0x26E\r
-#define EFI_IA32_MTRR_FIX4K_F8000 0x26F\r
-\r
-#define EFI_IA32_MCG_CAP 0x179\r
-#define EFI_IA32_MCG_CTL 0x17B\r
-#define EFI_IA32_MC0_CTL 0x400\r
-#define EFI_IA32_MC0_STATUS 0x401\r
-\r
-#define EFI_IA32_PERF_STATUS 0x198\r
-#define EFI_IA32_PERF_CTL 0x199\r
-\r
-#define EFI_CACHE_UNCACHEABLE 0\r
-#define EFI_CACHE_WRITECOMBINING 1\r
-#define EFI_CACHE_WRITETHROUGH 4\r
-#define EFI_CACHE_WRITEPROTECTED 5\r
-#define EFI_CACHE_WRITEBACK 6\r
-\r
-//\r
-// Combine f(FamilyId), m(Model), s(SteppingId) to a single 32 bit number\r
-//\r
-#define EfiMakeCpuVersion(f, m, s) \\r
- (((UINT32) (f) << 16) | ((UINT32) (m) << 8) | ((UINT32) (s)))\r
-\r
-VOID\r
-EFIAPI\r
-EfiHalt (\r
- VOID\r
- );\r
-\r
-/*++ \r
-Routine Description: \r
- Halt the Cpu \r
-Arguments: \r
- None \r
-Returns: \r
- None \r
---*/\r
-VOID\r
-EFIAPI\r
-EfiWbinvd (\r
- VOID\r
- );\r
-\r
-/*++ \r
-Routine Description: \r
- Write back and invalidate the Cpu cache\r
-Arguments: \r
- None \r
-Returns: \r
- None \r
---*/\r
-VOID\r
-EFIAPI\r
-EfiInvd (\r
- VOID\r
- );\r
-\r
-/*++ \r
-Routine Description: \r
- Invalidate the Cpu cache\r
-Arguments: \r
- None \r
-Returns: \r
- None \r
---*/\r
-VOID\r
-EFIAPI\r
-EfiCpuid (\r
- IN UINT32 RegisterInEax,\r
- OUT EFI_CPUID_REGISTER *Regs\r
- );\r
-\r
-/*++ \r
-Routine Description: \r
- Get the Cpu info by execute the CPUID instruction\r
-Arguments: \r
- RegisterInEax: -The input value to put into register EAX\r
- Regs: -The Output value \r
-Returns: \r
- None \r
---*/\r
-\r
-VOID\r
-EFIAPI\r
-EfiCpuidExt (\r
- IN UINT32 RegisterInEax,\r
- IN UINT32 CacheLevel,\r
- OUT EFI_CPUID_REGISTER *Regs\r
- )\r
-/*++ \r
-Routine Description: \r
- When RegisterInEax != 4, the functionality is the same as EfiCpuid.\r
- When RegisterInEax == 4, the function return the deterministic cache\r
- parameters by excuting the CPUID instruction\r
-Arguments: \r
- RegisterInEax: - The input value to put into register EAX\r
- CacheLevel: - The deterministic cache level\r
- Regs: - The Output value \r
-Returns: \r
- None \r
---*/\r
-;\r
-\r
-UINT64\r
-EFIAPI\r
-EfiReadMsr (\r
- IN UINT32 Index\r
- );\r
-\r
-/*++ \r
-Routine Description: \r
- Read Cpu MSR\r
-Arguments: \r
- Index: -The index value to select the register\r
- \r
-Returns: \r
- Return the read data \r
---*/\r
-VOID\r
-EFIAPI\r
-EfiWriteMsr (\r
- IN UINT32 Index,\r
- IN UINT64 Value\r
- );\r
-\r
-/*++ \r
-Routine Description: \r
- Write Cpu MSR\r
-Arguments: \r
- Index: -The index value to select the register\r
- Value: -The value to write to the selected register \r
-Returns: \r
- None \r
---*/\r
-UINT64\r
-EFIAPI\r
-EfiReadTsc (\r
- VOID\r
- );\r
-\r
-/*++ \r
-Routine Description: \r
- Read Time stamp\r
-Arguments: \r
- None \r
-Returns: \r
- Return the read data \r
---*/\r
-VOID\r
-EFIAPI\r
-EfiDisableCache (\r
- VOID\r
- );\r
-\r
-/*++ \r
-Routine Description: \r
- Writing back and invalidate the cache,then diable it\r
-Arguments: \r
- None \r
-Returns: \r
- None \r
---*/\r
-VOID\r
-EFIAPI\r
-EfiEnableCache (\r
- VOID\r
- );\r
-\r
-/*++ \r
-Routine Description: \r
- Invalidate the cache,then Enable it\r
-Arguments: \r
- None \r
-Returns: \r
- None \r
---*/\r
-UINT32\r
-EFIAPI\r
-EfiGetEflags (\r
- VOID\r
- );\r
-\r
-/*++ \r
-Routine Description: \r
- Get Eflags\r
-Arguments: \r
- None \r
-Returns: \r
- Return the Eflags value \r
---*/\r
-VOID\r
-EFIAPI\r
-EfiDisableInterrupts (\r
- VOID\r
- );\r
-\r
-/*++ \r
-Routine Description: \r
- Disable Interrupts\r
-Arguments: \r
- None \r
-Returns: \r
- None\r
---*/\r
-VOID\r
-EFIAPI\r
-EfiEnableInterrupts (\r
- VOID\r
- );\r
-\r
-/*++ \r
-Routine Description: \r
- Enable Interrupts\r
-Arguments: \r
- None \r
-Returns: \r
- None \r
---*/\r
-\r
-\r
-VOID\r
-EFIAPI\r
-EfiCpuVersion (\r
- IN UINT16 *FamilyId, OPTIONAL\r
- IN UINT8 *Model, OPTIONAL\r
- IN UINT8 *SteppingId, OPTIONAL\r
- IN UINT8 *Processor OPTIONAL\r
- )\r
-/*++\r
-\r
-Routine Description:\r
- Extract CPU detail version infomation\r
-\r
-Arguments:\r
- FamilyId - FamilyId, including ExtendedFamilyId\r
- Model - Model, including ExtendedModel\r
- SteppingId - SteppingId\r
- Processor - Processor\r
-\r
---*/\r
-;\r
-\r
-#endif\r
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