-#------------------------------------------------------------------------------
-#
-# Copyright (c) 2006 - 2009, Intel Corporation
-# All rights reserved. This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-# Module Name:
-#
-# Thunk16.S
-#
-# Abstract:
-#
-# Real mode thunk
-#
-#------------------------------------------------------------------------------
-
-#include <EdkIIGlueBase.h>
-
-.globl ASM_PFX(m16Start)
-.globl ASM_PFX(m16Size)
-.globl ASM_PFX(mThunk16Attr)
-.globl ASM_PFX(m16Gdt)
-.globl ASM_PFX(m16GdtrBase)
-.globl ASM_PFX(mTransition)
-.globl ASM_PFX(InternalAsmThunk16)
-
-# define the structure of IA32_REGS
-.equ _EDI, 0 #size 4
-.equ _ESI, 4 #size 4
-.equ _EBP, 8 #size 4
-.equ _ESP, 12 #size 4
-.equ _EBX, 16 #size 4
-.equ _EDX, 20 #size 4
-.equ _ECX, 24 #size 4
-.equ _EAX, 28 #size 4
-.equ _DS, 32 #size 2
-.equ _ES, 34 #size 2
-.equ _FS, 36 #size 2
-.equ _GS, 38 #size 2
-.equ _EFLAGS, 40 #size 8
-.equ _EIP, 48 #size 4
-.equ _CS, 52 #size 2
-.equ _SS, 54 #size 2
-.equ IA32_REGS_SIZE, 56
-
- .data
-
-ASM_PFX(m16Size): .word ASM_PFX(InternalAsmThunk16) - ASM_PFX(m16Start)
-ASM_PFX(mThunk16Attr): .word _ThunkAttr - ASM_PFX(m16Start)
-ASM_PFX(m16Gdt): .word ASM_PFX(NullSeg) - ASM_PFX(m16Start)
-ASM_PFX(m16GdtrBase): .word _16GdtrBase - ASM_PFX(m16Start)
-ASM_PFX(mTransition): .word _EntryPoint - ASM_PFX(m16Start)
-
- .text
-
-ASM_PFX(m16Start):
-
-SavedGdt: .space 10
-
-#------------------------------------------------------------------------------
-# _BackFromUserCode() takes control in real mode after 'retf' has been executed
-# by user code. It will be shadowed to somewhere in memory below 1MB.
-#------------------------------------------------------------------------------
-.globl ASM_PFX(BackFromUserCode)
-ASM_PFX(BackFromUserCode):
- #
- # The order of saved registers on the stack matches the order they appears
- # in IA32_REGS structure. This facilitates wrapper function to extract them
- # into that structure.
- #
- # Some instructions for manipulation of segment registers have to be written
- # in opcode since 64-bit MASM prevents accesses to those registers.
- #
- .byte 0x16 # push ss
- .byte 0xe # push cs
- .byte 0x66
- call L_Base # push eip
-L_Base:
- .byte 0x66
- pushq $0 # reserved high order 32 bits of EFlags
- .byte 0x66, 0x9c # pushfd actually
- cli # disable interrupts
- push %gs
- push %fs
- .byte 6 # push es
- .byte 0x1e # push ds
- .byte 0x66,0x60 # pushad
- .byte 0x66,0xba # mov edx, imm32
-_ThunkAttr: .space 4
- testb $THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15, %dl
- jz L_1
- movl $0x15cd2401,%eax # mov ax, 2401h & int 15h
- cli # disable interrupts
- jnc L_2
-L_1:
- testb $THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL, %dl
- jz L_2
- inb $0x92,%al
- orb $2,%al
- outb %al, $0x92 # deactivate A20M#
-L_2:
- movl %ss,%eax
- lea IA32_REGS_SIZE(%esp), %bp
- #
- # rsi in the following 2 instructions is indeed bp in 16-bit code
- #
- movw %bp, (_ESP - IA32_REGS_SIZE)(%rsi)
- .byte 0x66
- movl (_EIP - IA32_REGS_SIZE)(%rsi), %ebx
- shlw $4,%ax # shl eax, 4
- addw %ax,%bp # add ebp, eax
- movw %cs,%ax
- shlw $4,%ax
- lea (L_64BitCode - L_Base)(%ebx, %eax), %ax
- .byte 0x66,0x2e,0x89,0x87 # mov cs:[bx + (L_64Eip - L_Base)], eax
- .word L_64Eip - L_Base
- .byte 0x66,0xb8 # mov eax, imm32
-SavedCr4: .space 4
- movq %rax, %cr4
- #
- # rdi in the instruction below is indeed bx in 16-bit code
- #
- .byte 0x66,0x2e # 2eh is "cs:" segment override
- lgdt (SavedGdt - L_Base)(%rdi)
- .byte 0x66
- movl $0xc0000080,%ecx
- rdmsr
- orb $1,%ah
- wrmsr
- .byte 0x66,0xb8 # mov eax, imm32
-SavedCr0: .space 4
- movq %rax, %cr0
- .byte 0x66,0xea # jmp far cs:L_64Bit
-L_64Eip: .space 4
-SavedCs: .space 2
-L_64BitCode:
- .byte 0x90
- .byte 0x67,0xbc # mov esp, imm32
-SavedSp: .space 4 # restore stack
- nop
- ret
-
-_EntryPoint: .long ASM_PFX(ToUserCode) - ASM_PFX(m16Start)
- .word CODE16
-_16Gdtr: .word GDT_SIZE - 1
-_16GdtrBase: .quad ASM_PFX(NullSeg)
-_16Idtr: .word 0x3ff
- .long 0
-
-#------------------------------------------------------------------------------
-# _ToUserCode() takes control in real mode before passing control to user code.
-# It will be shadowed to somewhere in memory below 1MB.
-#------------------------------------------------------------------------------
-.globl ASM_PFX(ToUserCode)
-ASM_PFX(ToUserCode):
- movl %edx,%ss # set new segment selectors
- movl %edx,%ds
- movl %edx,%es
- movl %edx,%fs
- movl %edx,%gs
- .byte 0x66
- movl $0xc0000080,%ecx
- movq %rax, %cr0
- rdmsr
- andb $0b11111110, %ah
- wrmsr
- movq %rbp, %cr4
- movl %esi,%ss # set up 16-bit stack segment
- movw %bx,%sp # set up 16-bit stack pointer
- .byte 0x66 # make the following call 32-bit
- call L_Base1 # push eip
-L_Base1:
- popw %bp # ebp <- address of L_Base1
- pushq (IA32_REGS_SIZE + 2)(%esp)
- lea 0x0c(%rsi), %eax
- pushq %rax
- lret # execution begins at next instruction
-L_RealMode:
- .byte 0x66,0x2e # CS and operand size override
- lidt (_16Idtr - L_Base1)(%rsi)
- .byte 0x66,0x61 # popad
- .byte 0x1f # pop ds
- .byte 0x7 # pop es
- .byte 0x0f, 0xa1 # pop fs
- .byte 0x0f, 0xa9 # pop gs
- .byte 0x66, 0x9d # popfd
- leaw 4(%esp),%sp # skip high order 32 bits of EFlags
- .byte 0x66 # make the following retf 32-bit
- lret # transfer control to user code
-
-.equ CODE16, ASM_PFX(_16Code) - .
-.equ DATA16, ASM_PFX(_16Data) - .
-.equ DATA32, ASM_PFX(_32Data) - .
-
-ASM_PFX(NullSeg): .quad 0
-ASM_PFX(_16Code):
- .word -1
- .word 0
- .byte 0
- .byte 0x9b
- .byte 0x8f # 16-bit segment, 4GB limit
- .byte 0
-ASM_PFX(_16Data):
- .word -1
- .word 0
- .byte 0
- .byte 0x93
- .byte 0x8f # 16-bit segment, 4GB limit
- .byte 0
-ASM_PFX(_32Data):
- .word -1
- .word 0
- .byte 0
- .byte 0x93
- .byte 0xcf # 16-bit segment, 4GB limit
- .byte 0
-
-.equ GDT_SIZE, . - ASM_PFX(NullSeg)
-
-#------------------------------------------------------------------------------
-# IA32_REGISTER_SET *
-# EFIAPI
-# InternalAsmThunk16 (
-# IN IA32_REGISTER_SET *RegisterSet,
-# IN OUT VOID *Transition
-# );
-#------------------------------------------------------------------------------
-
-.globl ASM_PFX(InternalAsmThunk16)
-ASM_PFX(InternalAsmThunk16):
- pushq %rbp
- pushq %rbx
- pushq %rsi
- pushq %rdi
-
- movq %ds, %rbx
- pushq %rbx # Save ds segment register on the stack
- movq %es, %rbx
- pushq %rbx # Save es segment register on the stack
- movq %ss, %rbx
- pushq %rbx # Save ss segment register on the stack
-
- .byte 0x0f, 0xa0 #push fs
- .byte 0x0f, 0xa8 #push gs
- movq %rcx, %rsi
- movzwl _SS(%rsi), %r8d
- movl _ESP(%rsi), %edi
- lea -(IA32_REGS_SIZE + 4)(%edi), %rdi
- imul $16, %r8d, %eax
- movl %edi,%ebx # ebx <- stack for 16-bit code
- pushq $(IA32_REGS_SIZE / 4)
- addl %eax,%edi # edi <- linear address of 16-bit stack
- popq %rcx
- rep
- movsl # copy RegSet
- lea (SavedCr4 - ASM_PFX(m16Start))(%rdx), %ecx
- movl %edx,%eax # eax <- transition code address
- andl $0xf,%edx
- shll $12,%eax # segment address in high order 16 bits
- lea (_BackFromUserCode - ASM_PFX(m16Start))(%rdx), %ax
- stosl # [edi] <- return address of user code
- sgdt (SavedGdt - SavedCr4)(%rcx)
- sidt 0x50(%rsp)
- movq %cr0, %rax
- movl %eax, (SavedCr0 - SavedCr4)(%rcx)
- andl $0x7ffffffe,%eax # clear PE, PG bits
- movq %cr4, %rbp
- movl %ebp, (%rcx) # save CR4 in SavedCr4
- andl $0x300,%ebp # clear all but PCE and OSFXSR bits
- movl %r8d, %esi # esi <- 16-bit stack segment
- .byte 0x6a, DATA32
- popq %rdx
- lgdt (_16Gdtr - SavedCr4)(%rcx)
- movl %edx,%ss
- pushfq
- lea -8(%rdx), %edx
- lea L_RetFromRealMode, %r8
- pushq %r8
- movl %cs, %r8d
- movw %r8w, (SavedCs - SavedCr4)(%rcx)
- movl %esp, (SavedSp - SavedCr4)(%rcx)
- .byte 0xff, 0x69 # jmp (_EntryPoint - SavedCr4)(%rcx)
- .byte _EntryPoint - SavedCr4
-L_RetFromRealMode:
- popfq
- lidt 0x50(%rsp)
- lea -IA32_REGS_SIZE(%rbp), %eax
- .byte 0x0f, 0xa9 # pop gs
- .byte 0x0f, 0xa1 # pop fs
-
- popq %rbx
- movq %rbx, %ss
- popq %rbx
- movq %rbx, %es
- popq %rbx
- movq %rbx, %ds
-
- popq %rdi
- popq %rsi
- popq %rbx
- popq %rbp
-
- ret
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2006 - 2009, Intel Corporation\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Module Name:\r
+#\r
+# Thunk16.S\r
+#\r
+# Abstract:\r
+#\r
+# Real mode thunk\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#include <EdkIIGlueBase.h>\r
+\r
+.globl ASM_PFX(m16Start)\r
+.globl ASM_PFX(m16Size)\r
+.globl ASM_PFX(mThunk16Attr)\r
+.globl ASM_PFX(m16Gdt)\r
+.globl ASM_PFX(m16GdtrBase)\r
+.globl ASM_PFX(mTransition)\r
+.globl ASM_PFX(InternalAsmThunk16)\r
+\r
+# define the structure of IA32_REGS\r
+.equ _EDI, 0 #size 4\r
+.equ _ESI, 4 #size 4\r
+.equ _EBP, 8 #size 4\r
+.equ _ESP, 12 #size 4\r
+.equ _EBX, 16 #size 4\r
+.equ _EDX, 20 #size 4\r
+.equ _ECX, 24 #size 4\r
+.equ _EAX, 28 #size 4\r
+.equ _DS, 32 #size 2\r
+.equ _ES, 34 #size 2\r
+.equ _FS, 36 #size 2\r
+.equ _GS, 38 #size 2\r
+.equ _EFLAGS, 40 #size 8\r
+.equ _EIP, 48 #size 4\r
+.equ _CS, 52 #size 2\r
+.equ _SS, 54 #size 2\r
+.equ IA32_REGS_SIZE, 56\r
+\r
+ .data\r
+\r
+ASM_PFX(m16Size): .word ASM_PFX(InternalAsmThunk16) - ASM_PFX(m16Start)\r
+ASM_PFX(mThunk16Attr): .word _ThunkAttr - ASM_PFX(m16Start)\r
+ASM_PFX(m16Gdt): .word ASM_PFX(NullSeg) - ASM_PFX(m16Start)\r
+ASM_PFX(m16GdtrBase): .word _16GdtrBase - ASM_PFX(m16Start)\r
+ASM_PFX(mTransition): .word _EntryPoint - ASM_PFX(m16Start)\r
+\r
+ .text\r
+\r
+ASM_PFX(m16Start):\r
+\r
+SavedGdt: .space 10\r
+\r
+#------------------------------------------------------------------------------\r
+# _BackFromUserCode() takes control in real mode after 'retf' has been executed\r
+# by user code. It will be shadowed to somewhere in memory below 1MB.\r
+#------------------------------------------------------------------------------\r
+.globl ASM_PFX(BackFromUserCode)\r
+ASM_PFX(BackFromUserCode):\r
+ #\r
+ # The order of saved registers on the stack matches the order they appears\r
+ # in IA32_REGS structure. This facilitates wrapper function to extract them\r
+ # into that structure.\r
+ #\r
+ # Some instructions for manipulation of segment registers have to be written\r
+ # in opcode since 64-bit MASM prevents accesses to those registers.\r
+ #\r
+ .byte 0x16 # push ss\r
+ .byte 0xe # push cs\r
+ .byte 0x66\r
+ call L_Base # push eip\r
+L_Base: \r
+ .byte 0x66\r
+ pushq $0 # reserved high order 32 bits of EFlags\r
+ .byte 0x66, 0x9c # pushfd actually\r
+ cli # disable interrupts\r
+ push %gs\r
+ push %fs\r
+ .byte 6 # push es\r
+ .byte 0x1e # push ds\r
+ .byte 0x66,0x60 # pushad\r
+ .byte 0x66,0xba # mov edx, imm32\r
+_ThunkAttr: .space 4\r
+ testb $THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15, %dl\r
+ jz L_1\r
+ movl $0x15cd2401,%eax # mov ax, 2401h & int 15h\r
+ cli # disable interrupts\r
+ jnc L_2\r
+L_1: \r
+ testb $THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL, %dl\r
+ jz L_2\r
+ inb $0x92,%al\r
+ orb $2,%al\r
+ outb %al, $0x92 # deactivate A20M#\r
+L_2: \r
+ movl %ss,%eax\r
+ lea IA32_REGS_SIZE(%esp), %bp\r
+ #\r
+ # rsi in the following 2 instructions is indeed bp in 16-bit code\r
+ #\r
+ movw %bp, (_ESP - IA32_REGS_SIZE)(%rsi)\r
+ .byte 0x66\r
+ movl (_EIP - IA32_REGS_SIZE)(%rsi), %ebx\r
+ shlw $4,%ax # shl eax, 4\r
+ addw %ax,%bp # add ebp, eax\r
+ movw %cs,%ax\r
+ shlw $4,%ax\r
+ lea (L_64BitCode - L_Base)(%ebx, %eax), %ax\r
+ .byte 0x66,0x2e,0x89,0x87 # mov cs:[bx + (L_64Eip - L_Base)], eax\r
+ .word L_64Eip - L_Base\r
+ .byte 0x66,0xb8 # mov eax, imm32\r
+SavedCr4: .space 4\r
+ movq %rax, %cr4\r
+ #\r
+ # rdi in the instruction below is indeed bx in 16-bit code\r
+ #\r
+ .byte 0x66,0x2e # 2eh is "cs:" segment override\r
+ lgdt (SavedGdt - L_Base)(%rdi)\r
+ .byte 0x66\r
+ movl $0xc0000080,%ecx\r
+ rdmsr\r
+ orb $1,%ah\r
+ wrmsr\r
+ .byte 0x66,0xb8 # mov eax, imm32\r
+SavedCr0: .space 4\r
+ movq %rax, %cr0\r
+ .byte 0x66,0xea # jmp far cs:L_64Bit\r
+L_64Eip: .space 4\r
+SavedCs: .space 2\r
+L_64BitCode: \r
+ .byte 0x90\r
+ .byte 0x67,0xbc # mov esp, imm32\r
+SavedSp: .space 4 # restore stack\r
+ nop\r
+ ret\r
+\r
+_EntryPoint: .long ASM_PFX(ToUserCode) - ASM_PFX(m16Start)\r
+ .word CODE16\r
+_16Gdtr: .word GDT_SIZE - 1\r
+_16GdtrBase: .quad ASM_PFX(NullSeg)\r
+_16Idtr: .word 0x3ff\r
+ .long 0\r
+\r
+#------------------------------------------------------------------------------\r
+# _ToUserCode() takes control in real mode before passing control to user code.\r
+# It will be shadowed to somewhere in memory below 1MB.\r
+#------------------------------------------------------------------------------\r
+.globl ASM_PFX(ToUserCode)\r
+ASM_PFX(ToUserCode):\r
+ movl %edx,%ss # set new segment selectors\r
+ movl %edx,%ds\r
+ movl %edx,%es\r
+ movl %edx,%fs\r
+ movl %edx,%gs\r
+ .byte 0x66\r
+ movl $0xc0000080,%ecx\r
+ movq %rax, %cr0\r
+ rdmsr\r
+ andb $0b11111110, %ah \r
+ wrmsr\r
+ movq %rbp, %cr4\r
+ movl %esi,%ss # set up 16-bit stack segment\r
+ movw %bx,%sp # set up 16-bit stack pointer\r
+ .byte 0x66 # make the following call 32-bit\r
+ call L_Base1 # push eip\r
+L_Base1: \r
+ popw %bp # ebp <- address of L_Base1\r
+ pushq (IA32_REGS_SIZE + 2)(%esp)\r
+ lea 0x0c(%rsi), %eax\r
+ pushq %rax\r
+ lret # execution begins at next instruction\r
+L_RealMode: \r
+ .byte 0x66,0x2e # CS and operand size override\r
+ lidt (_16Idtr - L_Base1)(%rsi)\r
+ .byte 0x66,0x61 # popad\r
+ .byte 0x1f # pop ds\r
+ .byte 0x7 # pop es\r
+ .byte 0x0f, 0xa1 # pop fs\r
+ .byte 0x0f, 0xa9 # pop gs\r
+ .byte 0x66, 0x9d # popfd\r
+ leaw 4(%esp),%sp # skip high order 32 bits of EFlags\r
+ .byte 0x66 # make the following retf 32-bit\r
+ lret # transfer control to user code\r
+\r
+.equ CODE16, ASM_PFX(_16Code) - .\r
+.equ DATA16, ASM_PFX(_16Data) - .\r
+.equ DATA32, ASM_PFX(_32Data) - .\r
+\r
+ASM_PFX(NullSeg): .quad 0\r
+ASM_PFX(_16Code):\r
+ .word -1\r
+ .word 0\r
+ .byte 0\r
+ .byte 0x9b\r
+ .byte 0x8f # 16-bit segment, 4GB limit\r
+ .byte 0\r
+ASM_PFX(_16Data):\r
+ .word -1\r
+ .word 0\r
+ .byte 0\r
+ .byte 0x93\r
+ .byte 0x8f # 16-bit segment, 4GB limit\r
+ .byte 0\r
+ASM_PFX(_32Data):\r
+ .word -1\r
+ .word 0\r
+ .byte 0\r
+ .byte 0x93\r
+ .byte 0xcf # 16-bit segment, 4GB limit\r
+ .byte 0\r
+\r
+.equ GDT_SIZE, . - ASM_PFX(NullSeg)\r
+\r
+#------------------------------------------------------------------------------\r
+# IA32_REGISTER_SET *\r
+# EFIAPI\r
+# InternalAsmThunk16 (\r
+# IN IA32_REGISTER_SET *RegisterSet,\r
+# IN OUT VOID *Transition\r
+# );\r
+#------------------------------------------------------------------------------\r
+\r
+.globl ASM_PFX(InternalAsmThunk16)\r
+ASM_PFX(InternalAsmThunk16):\r
+ pushq %rbp\r
+ pushq %rbx\r
+ pushq %rsi\r
+ pushq %rdi\r
+ \r
+ movq %ds, %rbx\r
+ pushq %rbx # Save ds segment register on the stack\r
+ movq %es, %rbx\r
+ pushq %rbx # Save es segment register on the stack\r
+ movq %ss, %rbx\r
+ pushq %rbx # Save ss segment register on the stack\r
+\r
+ .byte 0x0f, 0xa0 #push fs\r
+ .byte 0x0f, 0xa8 #push gs\r
+ movq %rcx, %rsi\r
+ movzwl _SS(%rsi), %r8d\r
+ movl _ESP(%rsi), %edi\r
+ lea -(IA32_REGS_SIZE + 4)(%edi), %rdi\r
+ imul $16, %r8d, %eax \r
+ movl %edi,%ebx # ebx <- stack for 16-bit code\r
+ pushq $(IA32_REGS_SIZE / 4)\r
+ addl %eax,%edi # edi <- linear address of 16-bit stack\r
+ popq %rcx\r
+ rep\r
+ movsl # copy RegSet\r
+ lea (SavedCr4 - ASM_PFX(m16Start))(%rdx), %ecx\r
+ movl %edx,%eax # eax <- transition code address\r
+ andl $0xf,%edx\r
+ shll $12,%eax # segment address in high order 16 bits\r
+ lea (_BackFromUserCode - ASM_PFX(m16Start))(%rdx), %ax\r
+ stosl # [edi] <- return address of user code\r
+ sgdt (SavedGdt - SavedCr4)(%rcx) \r
+ sidt 0x50(%rsp)\r
+ movq %cr0, %rax\r
+ movl %eax, (SavedCr0 - SavedCr4)(%rcx)\r
+ andl $0x7ffffffe,%eax # clear PE, PG bits\r
+ movq %cr4, %rbp\r
+ movl %ebp, (%rcx) # save CR4 in SavedCr4\r
+ andl $0x300,%ebp # clear all but PCE and OSFXSR bits\r
+ movl %r8d, %esi # esi <- 16-bit stack segment\r
+ .byte 0x6a, DATA32\r
+ popq %rdx\r
+ lgdt (_16Gdtr - SavedCr4)(%rcx)\r
+ movl %edx,%ss\r
+ pushfq\r
+ lea -8(%rdx), %edx\r
+ lea L_RetFromRealMode, %r8\r
+ pushq %r8\r
+ movl %cs, %r8d\r
+ movw %r8w, (SavedCs - SavedCr4)(%rcx)\r
+ movl %esp, (SavedSp - SavedCr4)(%rcx)\r
+ .byte 0xff, 0x69 # jmp (_EntryPoint - SavedCr4)(%rcx)\r
+ .byte _EntryPoint - SavedCr4\r
+L_RetFromRealMode: \r
+ popfq\r
+ lidt 0x50(%rsp)\r
+ lea -IA32_REGS_SIZE(%rbp), %eax\r
+ .byte 0x0f, 0xa9 # pop gs\r
+ .byte 0x0f, 0xa1 # pop fs\r
+ \r
+ popq %rbx\r
+ movq %rbx, %ss\r
+ popq %rbx\r
+ movq %rbx, %es\r
+ popq %rbx\r
+ movq %rbx, %ds\r
+ \r
+ popq %rdi\r
+ popq %rsi\r
+ popq %rbx\r
+ popq %rbp\r
+\r
+ ret\r
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