Partially make EdkModulePkg pass intel IPF compiler with /W4 /WX switched on.

[mirror_edk2.git] / EdkModulePkg / Bus / Pci / Ehci / Dxe / EhciReg.c

diff --git a/EdkModulePkg/Bus/Pci/Ehci/Dxe/EhciReg.c b/EdkModulePkg/Bus/Pci/Ehci/Dxe/EhciReg.c
index 9ce816ecc97405473f27056d65a04197e8f75f4b..d5271c25b27b748930379d2b9d437e270a298437 100644 (file)
--- a/EdkModulePkg/Bus/Pci/Ehci/Dxe/EhciReg.c
+++ b/EdkModulePkg/Bus/Pci/Ehci/Dxe/EhciReg.c
@@ -22,6 +22,75 @@ Revision History
 #include "Ehci.h"\r
 \r
 \r
+VOID\r
+HostReset (\r
+  IN USB2_HC_DEV    *HcDev\r
+  )\r
+{\r
+  UINT32  Value;\r
+  UINT32  TimeOut;\r
+ \r
+  ReadEhcOperationalReg (\r
+    HcDev,\r
+    USBCMD,\r
+    &Value\r
+    );\r
+\r
+  Value = Value & (~USBCMD_RS);\r
+  WriteEhcOperationalReg (\r
+    HcDev,\r
+    USBCMD,\r
+    Value\r
+    );\r
+\r
+  TimeOut = 40;\r
+  while (TimeOut --) {\r
+    gBS->Stall (500);\r
+    ReadEhcOperationalReg (\r
+      HcDev,\r
+      USBSTS,\r
+      &Value\r
+      );\r
+    if ((Value & USBSTS_HCH) != 0) {\r
+      break;\r
+    }\r
+  }\r
+\r
+  if (TimeOut == 0) {\r
+    DEBUG((gEHCErrorLevel, "TimeOut for clearing Run/Stop bit\n"));\r
+  }\r
+\r
+  ReadEhcOperationalReg (\r
+    HcDev,\r
+    USBCMD,\r
+    &Value\r
+    );\r
+  Value = Value | USBCMD_HCRESET;\r
+  WriteEhcOperationalReg (\r
+    HcDev,\r
+    USBCMD,\r
+    Value\r
+    );\r
+\r
+  TimeOut = 40;\r
+  while (TimeOut --) {\r
+    gBS->Stall (500);\r
+    ReadEhcOperationalReg (\r
+      HcDev,\r
+      USBCMD,\r
+      &Value\r
+      );\r
+    if ((Value & USBCMD_HCRESET) == 0) {\r
+      break;\r
+    }\r
+  }\r
+\r
+  if (TimeOut == 0) {\r
+    DEBUG((gEHCErrorLevel, "TimeOut for Host Reset\n"));\r
+  }\r
+\r
+}\r
+\r
 EFI_STATUS\r
 ReadEhcCapabiltiyReg (\r
   IN USB2_HC_DEV             *HcDev,\r
@@ -82,12 +151,12 @@ Returns:
     \r
 --*/\r
 {\r
-  ASSERT (mUsbCapabilityLen);\r
+  ASSERT (HcDev->UsbCapabilityLen);\r
   return HcDev->PciIo->Mem.Read (\r
                              HcDev->PciIo,\r
                              EfiPciIoWidthUint32,\r
                              USB_BAR_INDEX,\r
-                             (UINT64) (OperationalRegAddr + mUsbCapabilityLen),\r
+                             (UINT64) (OperationalRegAddr + HcDev->UsbCapabilityLen),\r
                              1,\r
                              Data\r
                              );\r
@@ -118,17 +187,137 @@ Returns:
   \r
 --*/\r
 {\r
-  ASSERT (mUsbCapabilityLen);\r
+  ASSERT (HcDev->UsbCapabilityLen);\r
   return HcDev->PciIo->Mem.Write (\r
                              HcDev->PciIo,\r
                              EfiPciIoWidthUint32,\r
                              USB_BAR_INDEX,\r
-                             (UINT64) (OperationalRegAddr + mUsbCapabilityLen),\r
+                             (UINT64) (OperationalRegAddr + HcDev->UsbCapabilityLen),\r
                              1,\r
                              &Data\r
                              );\r
 }\r
 \r
+VOID\r
+ClearLegacySupport (\r
+  IN USB2_HC_DEV     *HcDev\r
+  )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+  Stop the legacy USB SMI\r
+\r
+Arguments:\r
+\r
+  HcDev - USB2_HC_DEV\r
+\r
+Returns:\r
+\r
+  EFI_SUCCESS       Success\r
+  EFI_DEVICE_ERROR  Fail\r
+\r
+--*/\r
+{\r
+  UINT32  EECP;\r
+  UINT32  Value;\r
+  UINT32  TimeOut;\r
+\r
+  ReadEhcCapabiltiyReg (\r
+    HcDev,\r
+    HCCPARAMS,\r
+    &EECP\r
+    );\r
+\r
+  EECP = (EECP >> 8) & 0xFF;\r
+\r
+  DEBUG ((gEHCDebugLevel, "EHCI: EECPBase = 0x%x\n", EECP));\r
+\r
+\r
+  HcDev->PciIo->Pci.Read (\r
+                     HcDev->PciIo,\r
+                     EfiPciIoWidthUint32,\r
+                     EECP,\r
+                     1,\r
+                     &Value \r
+                     );\r
+\r
+  DEBUG((gEHCDebugLevel, "EECP[0] = 0x%x\n", Value));\r
+\r
+  HcDev->PciIo->Pci.Read (\r
+                     HcDev->PciIo,\r
+                     EfiPciIoWidthUint32,\r
+                     EECP + 0x4,\r
+                     1,\r
+                     &Value \r
+                     );\r
+\r
+  DEBUG((gEHCDebugLevel, "EECP[4] = 0x%x\n", Value));\r
+\r
+  HcDev->PciIo->Pci.Read (\r
+                     HcDev->PciIo,\r
+                     EfiPciIoWidthUint32,\r
+                     EECP,\r
+                     1,\r
+                     &Value \r
+                     );\r
+\r
+  Value = Value | (0x1 << 24);\r
+  DEBUG((gEHCErrorLevel, "Value Written = 0x%x\n", Value));\r
+\r
+  HcDev->PciIo->Pci.Write (\r
+                     HcDev->PciIo,\r
+                     EfiPciIoWidthUint32,\r
+                     EECP,\r
+                     1,\r
+                     &Value \r
+                     );\r
+\r
+ TimeOut = 40;\r
+ while (TimeOut --) {\r
+   gBS->Stall (500);\r
+\r
+   HcDev->PciIo->Pci.Read (\r
+                      HcDev->PciIo,\r
+                      EfiPciIoWidthUint32,\r
+                      EECP,\r
+                      1,\r
+                      &Value \r
+                      );\r
+  if ((Value & 0x01010000) == 0x01000000) {\r
+    break;\r
+  }\r
+ }\r
+\r
+  if (TimeOut == 0) {\r
+    DEBUG((gEHCErrorLevel, "Timeout for getting HC OS Owned Semaphore\n" ));\r
+  } \r
+  \r
+  DEBUG((gEHCErrorLevel, "After Release Value\n" ));\r
+\r
+  HcDev->PciIo->Pci.Read (\r
+                     HcDev->PciIo,\r
+                     EfiPciIoWidthUint32,\r
+                     EECP,\r
+                     1,\r
+                     &Value \r
+                     );\r
+\r
+  DEBUG((gEHCDebugLevel, "EECP[0] = 0x%x\n", Value));\r
+\r
+  HcDev->PciIo->Pci.Read (\r
+                     HcDev->PciIo,\r
+                     EfiPciIoWidthUint32,\r
+                     EECP + 0x4,\r
+                     1,\r
+                     &Value \r
+                     );\r
+\r
+  DEBUG((gEHCDebugLevel, "EECP[4] = 0x%x\n", Value));\r
+\r
+\r
+}\r
+\r
 EFI_STATUS\r
 GetCapabilityLen (\r
   IN USB2_HC_DEV     *HcDev\r
@@ -158,9 +347,9 @@ Returns:
   Status = ReadEhcCapabiltiyReg (\r
              HcDev,\r
              CapabilityLenAddr,\r
-             &mUsbCapabilityLen\r
+             &(HcDev->UsbCapabilityLen)\r
              );\r
-  mUsbCapabilityLen = (UINT8) mUsbCapabilityLen;\r
+  HcDev->UsbCapabilityLen = (UINT8) HcDev->UsbCapabilityLen;\r
 \r
   return Status;\r
 }\r
@@ -815,7 +1004,7 @@ Returns:
 \r
   HcCapParamsAddr = HCCPARAMS;\r
 \r
-  ReadEhcOperationalReg (\r
+  ReadEhcCapabiltiyReg(\r
     HcDev,\r
     HcCapParamsAddr,\r
     &HcCapParamsReg\r
@@ -947,7 +1136,7 @@ Returns:
     &PortStatusControlReg\r
     );\r
 \r
-  return ((PortStatusControlReg & PORTSC_PED) ? TRUE : FALSE);\r
+  return ((BOOLEAN) ((PortStatusControlReg & PORTSC_PED) ? TRUE : FALSE));\r
 }\r
 \r
 BOOLEAN\r
@@ -1158,7 +1347,7 @@ Returns:
   //\r
   gBS->Stall (EHCI_CLEAR_PORT_RESET_RECOVERY_TIME);\r
 \r
-  return (IsEhcPortEnabled (HcDev, PortNum) ? TRUE : FALSE);\r
+  return ((BOOLEAN) (IsEhcPortEnabled (HcDev, PortNum) ? TRUE : FALSE));\r
 }\r
 \r
 EFI_STATUS\r