- ___________________________________________\r
- | | Command Block | Control Block |\r
- | Channel | Registers | Registers |\r
- |___________|_______________|_______________|\r
- | Primary | 1F0h - 1F7h | 3F6h - 3F7h |\r
- |___________|_______________|_______________|\r
- | Secondary | 170h - 177h | 376h - 377h |\r
- |___________|_______________|_______________|\r
- \r
- Table 1. Compatibility resource mappings\r
- \r
- b) In Native-PCI mode, IDE registers are mapped into IO space using the BARs\r
- in IDE controller's PCI Configuration Space, shown in the Table 2 below.\r
- ___________________________________________________\r
- | | Command Block | Control Block |\r
- | Channel | Registers | Registers |\r
- |___________|___________________|___________________|\r
- | Primary | BAR at offset 0x10| BAR at offset 0x14|\r
- |___________|___________________|___________________|\r
- | Secondary | BAR at offset 0x18| BAR at offset 0x1C|\r
- |___________|___________________|___________________|\r
- \r
- Table 2. BARs for Register Mapping\r
- Note: Refer to Intel ICH4 datasheet, Control Block Offset: 03F4h for \r
- primary, 0374h for secondary. So 2 bytes extra offset should be \r
- added to the base addresses read from BARs.\r
- \r
+ <pre>\r
+ ___________________________________________\r
+ | | Command Block | Control Block |\r
+ | Channel | Registers | Registers |\r
+ |___________|_______________|_______________|\r
+ | Primary | 1F0h - 1F7h | 3F6h - 3F7h |\r
+ |___________|_______________|_______________|\r
+ | Secondary | 170h - 177h | 376h - 377h |\r
+ |___________|_______________|_______________|\r
+\r
+ Table 1. Compatibility resource mappings\r
+ </pre>\r
+\r
+ b) In Native-PCI mode, IDE registers are mapped into IO space using the BARs\r
+ in IDE controller's PCI Configuration Space, shown in the Table 2 below.\r
+ <pre>\r
+ ___________________________________________________\r
+ | | Command Block | Control Block |\r
+ | Channel | Registers | Registers |\r
+ |___________|___________________|___________________|\r
+ | Primary | BAR at offset 0x10| BAR at offset 0x14|\r
+ |___________|___________________|___________________|\r
+ | Secondary | BAR at offset 0x18| BAR at offset 0x1C|\r
+ |___________|___________________|___________________|\r
+\r
+ Table 2. BARs for Register Mapping\r
+ </pre>\r
+ @note Refer to Intel ICH4 datasheet, Control Block Offset: 03F4h for \r
+ primary, 0374h for secondary. So 2 bytes extra offset should be \r
+ added to the base addresses read from BARs.\r
+\r