/** @file\r
- Copyright (c) 2006, Intel Corporation \r
+ Copyright (c) 2006 - 2007 Intel Corporation. <BR>\r
All rights reserved. This program and the accompanying materials \r
are licensed and made available under the terms and conditions of the BSD License \r
which accompanies this distribution. The full text of the license may be found at \r
IDEBusDriverBindingSupported,\r
IDEBusDriverBindingStart,\r
IDEBusDriverBindingStop,\r
- 0x10,\r
+ 0xa,\r
NULL,\r
NULL\r
};\r
}\r
\r
//\r
- // Clsoe protocol, don't use device path protocol in the .Support() function\r
+ // Close protocol, don't use device path protocol in the .Support() function\r
//\r
gBS->CloseProtocol (\r
Controller,\r
EFI_IDE_CONTROLLER_INIT_PROTOCOL *IdeInit;\r
BOOLEAN EnumAll;\r
BOOLEAN ChannelEnabled;\r
- UINT8 ChannelCount;\r
UINT8 MaxDevices;\r
EFI_IDENTIFY_DATA IdentifyData;\r
EFI_ATA_COLLECTIVE_MODE *SupportedModes;\r
}\r
\r
//\r
- // Save Enumall and ChannelCount. Step7.2\r
+ // Save Enumall. Step7.2\r
//\r
EnumAll = IdeInit->EnumAll;\r
- ChannelCount = IdeInit->ChannelCount;\r
\r
//\r
// Consume PCI I/O protocol. Note that the OpenProtocol with _GET_PROTOCOL\r
ZeroMem (IdeBlkIoDevicePtr, sizeof (IDE_BLK_IO_DEV));\r
\r
IdeBlkIoDevicePtr->Signature = IDE_BLK_IO_DEV_SIGNATURE;\r
- IdeBlkIoDevicePtr->Channel = IdeChannel;\r
- IdeBlkIoDevicePtr->Device = IdeDevice;\r
+ IdeBlkIoDevicePtr->Channel = (EFI_IDE_CHANNEL) IdeChannel;\r
+ IdeBlkIoDevicePtr->Device = (EFI_IDE_DEVICE) IdeDevice;\r
\r
//\r
// initialize Block IO interface's Media pointer\r
IdeBlkIoDevicePtr = NULL;\r
continue;\r
}\r
-\r
+ //\r
+ // Record Udma Mode\r
+ //\r
+ IdeBlkIoDevicePtr->UdmaMode.Valid = TRUE;\r
+ IdeBlkIoDevicePtr->UdmaMode.Mode = SupportedModes->UdmaMode.Mode;\r
EnableInterrupt (IdeBlkIoDevicePtr);\r
} else if (SupportedModes->MultiWordDmaMode.Valid) {\r
\r
//\r
// Record PIO mode used in private data\r
//\r
- IdeBlkIoDevicePtr->PioMode = SupportedModes->PioMode.Mode;\r
+ IdeBlkIoDevicePtr->PioMode = (ATA_PIO_MODE) SupportedModes->PioMode.Mode;\r
\r
//\r
// Set IDE controller Timing Blocks in the PCI Configuration Space\r