/*++\r
\r
-Copyright (c) 2006, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2006 - 2007, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
Module Name:\r
\r
PciOptionRomSupport.c\r
- \r
+\r
Abstract:\r
\r
PCI Bus Driver\r
\r
--*/\r
\r
-#include "PciBus.h"\r
+#include "pcibus.h"\r
#include "PciResourceSupport.h"\r
\r
+//\r
+// Min Max\r
+//\r
+#define EFI_MIN(a, b) (((a) < (b)) ? (a) : (b))\r
+#define EFI_MAX(a, b) (((a) > (b)) ? (a) : (b))\r
+\r
+\r
EFI_STATUS\r
GetOpRomInfo (\r
IN PCI_IO_DEVICE *PciIoDevice\r
PciRootBridgeIo = PciIoDevice->PciRootBridgeIo;\r
\r
//\r
- // offset is 48 if is not ppb\r
+ // offset is 0x30 if is not ppb\r
//\r
\r
//\r
AllOnes = 0xfffffffe;\r
Address = EFI_PCI_ADDRESS (Bus, Device, Function, RomBarIndex);\r
\r
- Status = PciRootBridgeIo->Pci.Write (\r
+ Status = PciRootBridgeIoWrite (\r
PciRootBridgeIo,\r
+ &PciIoDevice->Pci,\r
EfiPciWidthUint32,\r
Address,\r
1,\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
- \r
+\r
//\r
// read back\r
//\r
- Status = PciRootBridgeIo->Pci.Read (\r
+ Status = PciRootBridgeIoRead (\r
PciRootBridgeIo,\r
+ &PciIoDevice->Pci,\r
EfiPciWidthUint32,\r
Address,\r
1,\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
-\r
- AllOnes &= 0xFFFFFFFC;\r
- if ((AllOnes == 0) || (AllOnes == 0xFFFFFFFC)) {\r
+ //\r
+ // Bits [1, 10] are reserved\r
+ //\r
+ AllOnes &= 0xFFFFF800;\r
+ if ((AllOnes == 0) || (AllOnes == 0xFFFFF800)) {\r
return EFI_NOT_FOUND;\r
}\r
\r
PciIoDevice->RomSize = (UINT64) ((~AllOnes) + 1);\r
return EFI_SUCCESS;\r
-\r
}\r
\r
EFI_STATUS\r
UINT16 OffsetPcir;\r
UINT32 RomBarOffset;\r
UINT32 RomBar;\r
- UINT64 Temp;\r
EFI_STATUS retStatus;\r
BOOLEAN FirstCheck;\r
UINT8 *Image;\r
UINT64 RomSize;\r
UINT64 RomImageSize;\r
UINT8 *RomInMemory;\r
+ UINT8 CodeType;\r
\r
RomSize = PciDevice->RomSize;\r
\r
Indicator = 0;\r
RomImageSize = 0;\r
RomInMemory = NULL;\r
- Temp = 0;\r
+ CodeType = 0xFF;\r
\r
//\r
// Get the RomBarIndex\r
sizeof (PCI_DATA_STRUCTURE),\r
(UINT8 *) RomPcir\r
);\r
+ if (RomPcir->CodeType == PCI_CODE_TYPE_PCAT_IMAGE) {\r
+ CodeType = PCI_CODE_TYPE_PCAT_IMAGE;\r
+ }\r
Indicator = RomPcir->Indicator;\r
RomImageSize = RomImageSize + RomPcir->ImageLength * 512;\r
RomBarOffset = RomBarOffset + RomPcir->ImageLength * 512;\r
} while (((Indicator & 0x80) == 0x00) && ((RomBarOffset - RomBar) < RomSize));\r
\r
+ //\r
+ // Some Legacy Cards do not report the correct ImageLength so used the maximum\r
+ // of the legacy length and the PCIR Image Length\r
+ //\r
+ if (CodeType == PCI_CODE_TYPE_PCAT_IMAGE) {\r
+ RomImageSize = EFI_MAX(RomImageSize, (((EFI_LEGACY_EXPANSION_ROM_HEADER *)RomHeader)->Size512 * 512));\r
+ }\r
+\r
if (RomImageSize > 0) {\r
retStatus = EFI_SUCCESS;\r
Image = AllocatePool ((UINT32) RomImageSize);\r
// Clear all bars\r
//\r
for (Offset = 0x10; Offset <= 0x24; Offset += sizeof (UINT32)) {\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllZero);\r
+ PciIoWrite (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllZero);\r
}\r
\r
//\r
// enable its decoder\r
//\r
Value32 = RomBar | 0x1;\r
- PciIo->Pci.Write (\r
+ PciIoWrite (\r
PciIo,\r
(EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32,\r
RomBarIndex,\r
// disable rom decode\r
//\r
Value32 = 0xFFFFFFFE;\r
- PciIo->Pci.Write (\r
+ PciIoWrite (\r
PciIo,\r
(EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32,\r
RomBarIndex,\r