/*++\r
\r
-Copyright (c) 2006, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2006 - 2007, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
Module Name:\r
\r
PciResourceSupport.c\r
- \r
+\r
Abstract:\r
\r
PCI Bus Driver\r
case PciBarTypeMem32:\r
case PciBarTypePMem32:\r
\r
- PciIo->Pci.Write (\r
+ PciIoWrite (\r
PciIo,\r
EfiPciIoWidthUint32,\r
(Node->PciDev->PciBar[Node->Bar]).Offset,\r
\r
Address32 = (UINT32) (Address & 0x00000000FFFFFFFF);\r
\r
- PciIo->Pci.Write (\r
+ PciIoWrite (\r
PciIo,\r
EfiPciIoWidthUint32,\r
(Node->PciDev->PciBar[Node->Bar]).Offset,\r
\r
Address32 = (UINT32) RShiftU64 (Address, 32);\r
\r
- PciIo->Pci.Write (\r
+ PciIoWrite (\r
PciIo,\r
EfiPciIoWidthUint32,\r
(UINT8) ((Node->PciDev->PciBar[Node->Bar]).Offset + 4),\r
\r
case PPB_BAR_0:\r
case PPB_BAR_1:\r
- PciIo->Pci.Write (\r
+ PciIoWrite (\r
PciIo,\r
EfiPciIoWidthUint32,\r
(Node->PciDev->PciBar[Node->Bar]).Offset,\r
case PPB_IO_RANGE:\r
\r
Address32 = ((UINT32) (Address)) >> 8;\r
- PciIo->Pci.Write (\r
+ PciIoWrite (\r
PciIo,\r
EfiPciIoWidthUint8,\r
0x1C,\r
);\r
\r
Address32 >>= 8;\r
- PciIo->Pci.Write (\r
+ PciIoWrite (\r
PciIo,\r
EfiPciIoWidthUint16,\r
0x30,\r
\r
Address32 = (UINT32) (Address + Node->Length - 1);\r
Address32 = ((UINT32) (Address32)) >> 8;\r
- PciIo->Pci.Write (\r
+ PciIoWrite (\r
PciIo,\r
EfiPciIoWidthUint8,\r
0x1D,\r
);\r
\r
Address32 >>= 8;\r
- PciIo->Pci.Write (\r
+ PciIoWrite (\r
PciIo,\r
EfiPciIoWidthUint16,\r
0x32,\r
case PPB_MEM32_RANGE:\r
\r
Address32 = ((UINT32) (Address)) >> 16;\r
- PciIo->Pci.Write (\r
+ PciIoWrite (\r
PciIo,\r
EfiPciIoWidthUint16,\r
0x20,\r
\r
Address32 = (UINT32) (Address + Node->Length - 1);\r
Address32 = ((UINT32) (Address32)) >> 16;\r
- PciIo->Pci.Write (\r
+ PciIoWrite (\r
PciIo,\r
EfiPciIoWidthUint16,\r
0x22,\r
case PPB_PMEM64_RANGE:\r
\r
Address32 = ((UINT32) (Address)) >> 16;\r
- PciIo->Pci.Write (\r
+ PciIoWrite (\r
PciIo,\r
EfiPciIoWidthUint16,\r
0x24,\r
\r
Address32 = (UINT32) (Address + Node->Length - 1);\r
Address32 = ((UINT32) (Address32)) >> 16;\r
- PciIo->Pci.Write (\r
+ PciIoWrite (\r
PciIo,\r
EfiPciIoWidthUint16,\r
0x26,\r
);\r
\r
Address32 = (UINT32) RShiftU64 (Address, 32);\r
- PciIo->Pci.Write (\r
+ PciIoWrite (\r
PciIo,\r
EfiPciIoWidthUint32,\r
0x28,\r
);\r
\r
Address32 = (UINT32) RShiftU64 ((Address + Node->Length - 1), 32);\r
- PciIo->Pci.Write (\r
+ PciIoWrite (\r
PciIo,\r
EfiPciIoWidthUint32,\r
0x2C,\r
switch (Node->Bar) {\r
\r
case P2C_BAR_0:\r
- PciIo->Pci.Write (\r
+ PciIoWrite (\r
PciIo,\r
EfiPciIoWidthUint32,\r
(Node->PciDev->PciBar[Node->Bar]).Offset,\r
break;\r
\r
case P2C_MEM_1:\r
- PciIo->Pci.Write (\r
+ PciIoWrite (\r
PciIo,\r
EfiPciIoWidthUint32,\r
0x1c,\r
);\r
\r
TempAddress = Address + Node->Length - 1;\r
- PciIo->Pci.Write (\r
+ PciIoWrite (\r
PciIo,\r
EfiPciIoWidthUint32,\r
0x20,\r
//\r
// Set non-prefetchable bit\r
//\r
- PciIo->Pci.Read (\r
+ PciIoRead (\r
PciIo,\r
EfiPciIoWidthUint16,\r
0x3e,\r
);\r
\r
BridgeControl &= 0xfeff;\r
- PciIo->Pci.Write (\r
+ PciIoWrite (\r
PciIo,\r
EfiPciIoWidthUint16,\r
0x3e,\r
//\r
// Set pre-fetchable bit\r
//\r
- PciIo->Pci.Read (\r
+ PciIoRead (\r
PciIo,\r
EfiPciIoWidthUint16,\r
0x3e,\r
);\r
\r
BridgeControl |= 0x0100;\r
- PciIo->Pci.Write (\r
+ PciIoWrite (\r
PciIo,\r
EfiPciIoWidthUint16,\r
0x3e,\r
break;\r
\r
case P2C_MEM_2:\r
- PciIo->Pci.Write (\r
+ PciIoWrite (\r
PciIo,\r
EfiPciIoWidthUint32,\r
0x24,\r
\r
TempAddress = Address + Node->Length - 1;\r
\r
- PciIo->Pci.Write (\r
+ PciIoWrite (\r
PciIo,\r
EfiPciIoWidthUint32,\r
0x28,\r
//\r
// Set non-prefetchable bit\r
//\r
- PciIo->Pci.Read (\r
+ PciIoRead (\r
PciIo,\r
EfiPciIoWidthUint16,\r
0x3e,\r
);\r
\r
BridgeControl &= 0xfdff;\r
- PciIo->Pci.Write (\r
+ PciIoWrite (\r
PciIo,\r
EfiPciIoWidthUint16,\r
0x3e,\r
//\r
// Set pre-fetchable bit\r
//\r
- PciIo->Pci.Read (\r
+ PciIoRead (\r
PciIo,\r
EfiPciIoWidthUint16,\r
0x3e,\r
);\r
\r
BridgeControl |= 0x0200;\r
- PciIo->Pci.Write (\r
+ PciIoWrite (\r
PciIo,\r
EfiPciIoWidthUint16,\r
0x3e,\r
break;\r
\r
case P2C_IO_1:\r
- PciIo->Pci.Write (\r
+ PciIoWrite (\r
PciIo,\r
EfiPciIoWidthUint32,\r
0x2c,\r
&Address\r
);\r
TempAddress = Address + Node->Length - 1;\r
- PciIo->Pci.Write (\r
+ PciIoWrite (\r
PciIo,\r
EfiPciIoWidthUint32,\r
0x30,\r
break;\r
\r
case P2C_IO_2:\r
- PciIo->Pci.Write (\r
+ PciIoWrite (\r
PciIo,\r
EfiPciIoWidthUint32,\r
0x34,\r
);\r
\r
TempAddress = Address + Node->Length - 1;\r
- PciIo->Pci.Write (\r
+ PciIoWrite (\r
PciIo,\r
EfiPciIoWidthUint32,\r
0x38,\r