EmbeddedPkg/Lan9118Dxe: add LAN9118 MMIO wrappers

[mirror_edk2.git] / EmbeddedPkg / Drivers / Lan9118Dxe / Lan9118DxeHw.h

diff --git a/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeHw.h b/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeHw.h
index 9e89d274599fa4583cf8e8abf36355a3cc0efb60..11895849a49ce21bfb110bdab4a02c7985f73d9a 100644 (file)
--- a/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeHw.h
+++ b/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeHw.h
@@ -57,6 +57,77 @@
 #define LAN9118_E2P_CMD                       (0x000000B0 + LAN9118_BA)    // EEPROM Command\r
 #define LAN9118_E2P_DATA                      (0x000000B4 + LAN9118_BA)    // EEPROM Data\r
 \r
+/*\r
+ * Required delays following write cycles (number of BYTE_TEST reads)\r
+ * Taken from Table 6.1 in Revision 1.5 (07-11-08) of the LAN9118 datasheet.\r
+ * Where no delay listed, 0 has been assumed.\r
+ */\r
+#define LAN9118_RX_DATA_WR_DELAY              0\r
+#define LAN9118_RX_STATUS_WR_DELAY            0\r
+#define LAN9118_RX_STATUS_PEEK_WR_DELAY       0\r
+#define LAN9118_TX_DATA_WR_DELAY              0\r
+#define LAN9118_TX_STATUS_WR_DELAY            0\r
+#define LAN9118_TX_STATUS_PEEK_WR_DELAY       0\r
+#define LAN9118_ID_REV_WR_DELAY               0\r
+#define LAN9118_IRQ_CFG_WR_DELAY              3\r
+#define LAN9118_INT_STS_WR_DELAY              2\r
+#define LAN9118_INT_EN_WR_DELAY               1\r
+#define LAN9118_BYTE_TEST_WR_DELAY            0\r
+#define LAN9118_FIFO_INT_WR_DELAY             1\r
+#define LAN9118_RX_CFG_WR_DELAY               1\r
+#define LAN9118_TX_CFG_WR_DELAY               1\r
+#define LAN9118_HW_CFG_WR_DELAY               1\r
+#define LAN9118_RX_DP_CTL_WR_DELAY            1\r
+#define LAN9118_RX_FIFO_INF_WR_DELAY          0\r
+#define LAN9118_TX_FIFO_INF_WR_DELAY          3\r
+#define LAN9118_PMT_CTRL_WR_DELAY             7\r
+#define LAN9118_GPIO_CFG_WR_DELAY             1\r
+#define LAN9118_GPT_CFG_WR_DELAY              1\r
+#define LAN9118_GPT_CNT_WR_DELAY              3\r
+#define LAN9118_WORD_SWAP_WR_DELAY            1\r
+#define LAN9118_FREE_RUN_WR_DELAY             4\r
+#define LAN9118_RX_DROP_WR_DELAY              0\r
+#define LAN9118_MAC_CSR_CMD_WR_DELAY          1\r
+#define LAN9118_MAC_CSR_DATA_WR_DELAY         1\r
+#define LAN9118_AFC_CFG_WR_DELAY              1\r
+#define LAN9118_E2P_CMD_WR_DELAY              1\r
+#define LAN9118_E2P_DATA_WR_DELAY             1\r
+\r
+/*\r
+ * Required delays following read cycles (number of BYTE_TEST reads)\r
+ * Taken from Table 6.2 in Revision 1.5 (07-11-08) of the LAN9118 datasheet.\r
+ * Where no delay listed, 0 has been assumed.\r
+ */\r
+#define LAN9118_RX_DATA_RD_DELAY              3\r
+#define LAN9118_RX_STATUS_RD_DELAY            3\r
+#define LAN9118_RX_STATUS_PEEK_RD_DELAY       0\r
+#define LAN9118_TX_DATA_RD_DELAY              0\r
+#define LAN9118_TX_STATUS_RD_DELAY            3\r
+#define LAN9118_TX_STATUS_PEEK_RD_DELAY       0\r
+#define LAN9118_ID_REV_RD_DELAY               0\r
+#define LAN9118_IRQ_CFG_RD_DELAY              0\r
+#define LAN9118_INT_STS_RD_DELAY              0\r
+#define LAN9118_INT_EN_RD_DELAY               0\r
+#define LAN9118_BYTE_TEST_RD_DELAY            0\r
+#define LAN9118_FIFO_INT_RD_DELAY             0\r
+#define LAN9118_RX_CFG_RD_DELAY               0\r
+#define LAN9118_TX_CFG_RD_DELAY               0\r
+#define LAN9118_HW_CFG_RD_DELAY               0\r
+#define LAN9118_RX_DP_CTL_RD_DELAY            0\r
+#define LAN9118_RX_FIFO_INF_RD_DELAY          0\r
+#define LAN9118_TX_FIFO_INF_RD_DELAY          0\r
+#define LAN9118_PMT_CTRL_RD_DELAY             0\r
+#define LAN9118_GPIO_CFG_RD_DELAY             0\r
+#define LAN9118_GPT_CFG_RD_DELAY              0\r
+#define LAN9118_GPT_CNT_RD_DELAY              0\r
+#define LAN9118_WORD_SWAP_RD_DELAY            0\r
+#define LAN9118_FREE_RUN_RD_DELAY             0\r
+#define LAN9118_RX_DROP_RD_DELAY              4\r
+#define LAN9118_MAC_CSR_CMD_RD_DELAY          0\r
+#define LAN9118_MAC_CSR_DATA_RD_DELAY         0\r
+#define LAN9118_AFC_CFG_RD_DELAY              0\r
+#define LAN9118_E2P_CMD_RD_DELAY              0\r
+#define LAN9118_E2P_DATA_RD_DELAY             0\r
 \r
 // Receiver Status bits\r
 #define RXSTATUS_CRC_ERROR                    BIT1                      // Cyclic Redundancy Check Error\r