\r
#include "Lan9118Dxe.h"\r
\r
-STATIC EFI_MAC_ADDRESS mZeroMac = { 0 };\r
+STATIC EFI_MAC_ADDRESS mZeroMac = { { 0 } };\r
\r
/**\r
This internal function reverses bits for 32bit data.\r
\r
// Write to Eeprom command register\r
MmioWrite32 (LAN9118_E2P_CMD, EepromCmd);\r
- gBS->Stall (LAN9118_STALL);\r
+ MemoryFence();\r
\r
// Wait until operation has completed\r
while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
\r
// Write to Eeprom command register\r
MmioWrite32 (LAN9118_E2P_CMD, EepromCmd);\r
- gBS->Stall (LAN9118_STALL);\r
+ MemoryFence();\r
\r
// Wait until operation has completed\r
while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
(UINT32)(Mac->Addr[4] & 0xFF) |\r
((Mac->Addr[5] & 0xFF) << 8)\r
);\r
-\r
- CopyMem (&Snp->Mode->CurrentAddress, &Mac, NET_ETHER_ADDR_LEN);\r
}\r
\r
VOID\r
if (((MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PM_MODE_MASK) >> 12) != 0) {\r
DEBUG ((DEBUG_NET, "Waking from reduced power state.\n"));\r
MmioWrite32 (LAN9118_BYTE_TEST, 0xFFFFFFFF);\r
- gBS->Stall (LAN9118_STALL);\r
+ MemoryFence();\r
}\r
\r
// Check that device is active\r
Timeout = 20;\r
while ((MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_READY) == 0 && --Timeout) {\r
gBS->Stall (LAN9118_STALL);\r
+ MemoryFence();\r
}\r
if (!Timeout) {\r
return EFI_TIMEOUT;\r
Timeout = 20;\r
while ((MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY) && --Timeout){\r
gBS->Stall (LAN9118_STALL);\r
+ MemoryFence();\r
}\r
if (!Timeout) {\r
return EFI_TIMEOUT;\r
DEBUG ((EFI_D_WARN, "Warning: using driver-default MAC address\n"));\r
DefaultMacAddress = FixedPcdGet64 (PcdLan9118DefaultMacAddress);\r
Lan9118SetMacAddress((EFI_MAC_ADDRESS *) &DefaultMacAddress, Snp);\r
+ CopyMem (&Snp->Mode->CurrentAddress, &DefaultMacAddress, NET_ETHER_ADDR_LEN);\r
}\r
} else {\r
// Store the MAC address that was loaded from EEPROM\r
\r
// Write the configuration\r
MmioWrite32 (LAN9118_HW_CFG, HwConf);\r
- gBS->Stall (LAN9118_STALL);\r
+ MemoryFence();\r
\r
// Wait for reset to complete\r
while (MmioRead32 (LAN9118_HW_CFG) & HWCFG_SRST) {\r
\r
+ MemoryFence();\r
gBS->Stall (LAN9118_STALL);\r
ResetTime += 1;\r
\r
\r
\r
// Perform PHY software reset\r
-INT32\r
+EFI_STATUS\r
PhySoftReset (\r
UINT32 Flags,\r
EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
)\r
{\r
UINT32 PmtCtrl = 0;\r
- UINT32 LinkTo = 0;\r
\r
// PMT PHY reset takes precedence over BCR\r
if (Flags & PHY_RESET_PMT) {\r
\r
// Wait for completion\r
while (MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PHY_RST) {\r
- gBS->Stall (LAN9118_STALL);\r
+ MemoryFence();\r
}\r
// PHY Basic Control Register reset\r
- } else if (Flags & PHY_RESET_PMT) {\r
+ } else if (Flags & PHY_RESET_BCR) {\r
IndirectPHYWrite32 (PHY_INDEX_BASIC_CTRL, PHYCR_RESET);\r
\r
// Wait for completion\r
while (IndirectPHYRead32 (PHY_INDEX_BASIC_CTRL) & PHYCR_RESET) {\r
- gBS->Stall (LAN9118_STALL);\r
- }\r
- }\r
-\r
- // Check the link status\r
- if (Flags & PHY_RESET_CHECK_LINK) {\r
- LinkTo = 100000; // 2 second (could be 50% more)\r
- while (EFI_ERROR (CheckLinkStatus (0, Snp)) && (LinkTo > 0)) {\r
- gBS->Stall (LAN9118_STALL);\r
- LinkTo--;\r
- }\r
-\r
- // Timed out\r
- if (LinkTo <= 0) {\r
- return -1;\r
+ MemoryFence();\r
}\r
}\r
\r
MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);\r
}\r
\r
- return 0;\r
+ return EFI_SUCCESS;\r
}\r
\r
\r
\r
// Write the configuration\r
MmioWrite32 (LAN9118_GPIO_CFG, GpioConf);\r
- gBS->Stall (LAN9118_STALL);\r
+ MemoryFence();\r
}\r
\r
return EFI_SUCCESS;\r
// Check that link is up first\r
if ((PhyStatus & PHYSTS_LINK_STS) == 0) {\r
// Wait until it is up or until Time Out\r
- TimeOut = 2000;\r
+ TimeOut = FixedPcdGet32 (PcdLan9118DefaultNegotiationTimeout) / LAN9118_STALL;\r
while ((IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS) & PHYSTS_LINK_STS) == 0) {\r
+ MemoryFence();\r
gBS->Stall (LAN9118_STALL);\r
TimeOut--;\r
if (!TimeOut) {\r
TxCfg = MmioRead32 (LAN9118_TX_CFG);\r
TxCfg |= TXCFG_TXS_DUMP | TXCFG_TXD_DUMP;\r
MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
- gBS->Stall (LAN9118_STALL);\r
+ MemoryFence();\r
}\r
\r
// Check if already stopped\r
if (TxCfg & TXCFG_TX_ON) {\r
TxCfg |= TXCFG_STOP_TX;\r
MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
- gBS->Stall (LAN9118_STALL);\r
+ MemoryFence();\r
\r
// Wait for Tx to finish transmitting\r
while (MmioRead32 (LAN9118_TX_CFG) & TXCFG_STOP_TX);\r
RxCfg = MmioRead32 (LAN9118_RX_CFG);\r
RxCfg |= RXCFG_RX_DUMP;\r
MmioWrite32 (LAN9118_RX_CFG, RxCfg);\r
- gBS->Stall (LAN9118_STALL);\r
+ MemoryFence();\r
\r
while (MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP);\r
}\r
TxCfg = MmioRead32 (LAN9118_TX_CFG);\r
TxCfg |= TXCFG_TXS_DUMP | TXCFG_TXD_DUMP;\r
MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
- gBS->Stall (LAN9118_STALL);\r
+ MemoryFence();\r
}\r
\r
// Check if tx was started from MAC and enable if not\r
if (Flags & START_TX_MAC) {\r
MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);\r
- gBS->Stall (LAN9118_STALL);\r
+ MemoryFence();\r
if ((MacCsr & MACCR_TX_EN) == 0) {\r
MacCsr |= MACCR_TX_EN;\r
IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);\r
- gBS->Stall (LAN9118_STALL);\r
+ MemoryFence();\r
}\r
}\r
\r
// Check if tx was started from TX_CFG and enable if not\r
if (Flags & START_TX_CFG) {\r
TxCfg = MmioRead32 (LAN9118_TX_CFG);\r
- gBS->Stall (LAN9118_STALL);\r
+ MemoryFence();\r
if ((TxCfg & TXCFG_TX_ON) == 0) {\r
TxCfg |= TXCFG_TX_ON;\r
MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
- gBS->Stall (LAN9118_STALL);\r
+ MemoryFence();\r
}\r
}\r
\r
RxCfg = MmioRead32 (LAN9118_RX_CFG);\r
RxCfg |= RXCFG_RX_DUMP;\r
MmioWrite32 (LAN9118_RX_CFG, RxCfg);\r
- gBS->Stall (LAN9118_STALL);\r
+ MemoryFence();\r
\r
while (MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP);\r
}\r
\r
MacCsr |= MACCR_RX_EN;\r
IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);\r
- gBS->Stall (LAN9118_STALL);\r
+ MemoryFence();\r
}\r
\r
return EFI_SUCCESS;\r
HwConf &= ~(0xF0000);\r
HwConf |= ((TxFifoOption & 0xF) << 16);\r
MmioWrite32 (LAN9118_HW_CFG, HwConf);\r
- gBS->Stall (LAN9118_STALL);\r
+ MemoryFence();\r
\r
return EFI_SUCCESS;\r
}\r