--- /dev/null
+/** @file\r
+* Header containing the structure specific to the Silicon Image I3132 Sata PCI card\r
+*\r
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#ifndef __SATASII3132_H\r
+#define __SATASII3132_H\r
+\r
+#include <PiDxe.h>\r
+\r
+#include <Protocol/AtaPassThru.h>\r
+#include <Protocol/PciIo.h>\r
+\r
+#include <Library/UefiLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+\r
+#include <IndustryStandard/Pci.h>\r
+\r
+#define SATA_SII3132_DEVICE_ID 0x3132\r
+#define SATA_SII3132_VENDOR_ID 0x1095\r
+\r
+#define SII3132_PORT_SIGNATURE_PMP 0x96690101\r
+#define SII3132_PORT_SIGNATURE_ATAPI 0xEB140101\r
+#define SII3132_PORT_SIGNATURE_ATA 0x00000101\r
+\r
+/*\r
+ * Silicon Image SiI3132 Registers\r
+ */\r
+#define SII3132_GLOBAL_CONTROL_REG 0x40\r
+#define SII3132_GLOBAL_FLASHADDR_REG 0x70\r
+\r
+#define SII3132_PORT_STATUS_REG 0x1000\r
+#define SII3132_PORT_CONTROLSET_REG 0x1000\r
+#define SII3132_PORT_CONTROLCLEAR_REG 0x1004\r
+#define SII3132_PORT_INTSTATUS_REG 0x1008\r
+#define SII3132_PORT_ENABLEINT_REG 0x1010\r
+#define SII3132_PORT_INTCLEAR_REG 0x1014\r
+#define SII3132_PORT_32BITACTIVADDR_REG 0x101C\r
+#define SII3132_PORT_CMDEXECFIFO_REG 0x1020\r
+#define SII3132_PORT_CMDERROR_REG 0x1024\r
+#define SII3132_PORT_ERRCOUNTDECODE 0x1040\r
+#define SII3132_PORT_ERRCOUNTCRC 0x1044\r
+#define SII3132_PORT_ERRCOUNTHANDSHAKE 0x1048\r
+#define SII3132_PORT_SLOTSTATUS_REG 0x1800\r
+#define SII3132_PORT_CMDACTIV_REG 0x1C00\r
+#define SII3132_PORT_SSTATUS_REG 0x1F04\r
+\r
+#define SII3132_PORT_CONTROL_RESET (1 << 0)\r
+#define SII3132_PORT_DEVICE_RESET (1 << 1)\r
+#define SII3132_PORT_CONTROL_INT (1 << 2)\r
+#define SII3132_PORT_CONTROL_32BITACTIVATION (1 << 10)\r
+\r
+#define SII3132_PORT_STATUS_PORTREADY 0x80000000\r
+\r
+#define SII3132_PORT_INT_CMDCOMPL (1 << 0)\r
+#define SII3132_PORT_INT_CMDERR (1 << 1)\r
+#define SII3132_PORT_INT_PORTRDY (1 << 2)\r
+\r
+#define SATA_SII3132_MAXPORT 2\r
+\r
+#define PRB_CTRL_ATA 0x0\r
+#define PRB_CTRL_PROT_OVERRIDE 0x1\r
+#define PRB_CTRL_RESTRANSMIT 0x2\r
+#define PRB_CTRL_EXT_CMD 0x4\r
+#define PRB_CTRL_RCV 0x8\r
+#define PRB_CTRL_PKT_READ 0x10\r
+#define PRB_CTRL_PKT_WRITE 0x20\r
+#define PRB_CTRL_INT_MASK 0x40\r
+#define PRB_CTRL_SRST 0x80\r
+\r
+#define PRB_PROT_PACKET 0x01\r
+#define PRB_PROT_LEGACY_QUEUE 0x02\r
+#define PRB_PROT_NATIVE_QUEUE 0x04\r
+#define PRB_PROT_READ 0x08\r
+#define PRB_PROT_WRITE 0x10\r
+#define PRB_PROT_TRANSPARENT 0x20\r
+\r
+#define SGE_XCF (1 << 28)\r
+#define SGE_DRD (1 << 29)\r
+#define SGE_LNK (1 << 30)\r
+#define SGE_TRM 0x80000000\r
+\r
+typedef struct _SATA_SI3132_SGE {\r
+ UINT32 DataAddressLow;\r
+ UINT32 DataAddressHigh;\r
+ UINT32 DataCount;\r
+ UINT32 Attributes;\r
+} SATA_SI3132_SGE;\r
+\r
+typedef struct _SATA_SI3132_FIS {\r
+ UINT8 FisType;\r
+ UINT8 Control;\r
+ UINT8 Command;\r
+ UINT8 Features;\r
+ UINT8 Fis[5 * 4];\r
+} SATA_SI3132_FIS;\r
+\r
+typedef struct _SATA_SI3132_PRB {\r
+ UINT16 Control;\r
+ UINT16 ProtocolOverride;\r
+ UINT32 RecTransCount;\r
+ SATA_SI3132_FIS Fis;\r
+ SATA_SI3132_SGE Sge[2];\r
+} SATA_SI3132_PRB;\r
+\r
+typedef struct _SATA_SI3132_DEVICE {\r
+ LIST_ENTRY Link; // This attribute must be the first entry of this structure (to avoid pointer computation)\r
+ UINTN Index;\r
+ struct _SATA_SI3132_PORT *Port; //Parent Port\r
+ UINT32 BlockSize;\r
+} SATA_SI3132_DEVICE;\r
+\r
+typedef struct _SATA_SI3132_PORT {\r
+ UINTN Index;\r
+ UINTN RegBase;\r
+ struct _SATA_SI3132_INSTANCE *Instance;\r
+\r
+ //TODO: Support Port multiplier\r
+ LIST_ENTRY Devices;\r
+\r
+ SATA_SI3132_PRB* HostPRB;\r
+ EFI_PHYSICAL_ADDRESS PhysAddrHostPRB;\r
+ VOID* PciAllocMappingPRB;\r
+} SATA_SI3132_PORT;\r
+\r
+typedef struct _SATA_SI3132_INSTANCE {\r
+ UINTN Signature;\r
+\r
+ SATA_SI3132_PORT Ports[SATA_SII3132_MAXPORT];\r
+\r
+ EFI_ATA_PASS_THRU_PROTOCOL AtaPassThruProtocol;\r
+\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+} SATA_SI3132_INSTANCE;\r
+\r
+#define SATA_SII3132_SIGNATURE SIGNATURE_32('s', 'i', '3', '2')\r
+#define INSTANCE_FROM_ATAPASSTHRU_THIS(a) CR(a, SATA_SI3132_INSTANCE, AtaPassThruProtocol, SATA_SII3132_SIGNATURE)\r
+\r
+#define SATA_GLOBAL_READ32(Offset, Value) PciIo->Mem.Read (PciIo, EfiPciIoWidthUint32, 0, Offset, 1, Value)\r
+#define SATA_GLOBAL_WRITE32(Offset, Value) { UINT32 Value32 = Value; PciIo->Mem.Write (PciIo, EfiPciIoWidthUint32, 0, Offset, 1, &Value32); }\r
+\r
+#define SATA_PORT_READ32(Offset, Value) PciIo->Mem.Read (PciIo, EfiPciIoWidthUint32, 1, Offset, 1, Value)\r
+#define SATA_PORT_WRITE32(Offset, Value) { UINT32 Value32 = Value; PciIo->Mem.Write (PciIo, EfiPciIoWidthUint32, 1, Offset, 1, &Value32); }\r
+\r
+#define SATA_TRACE(txt) DEBUG((EFI_D_VERBOSE, "ARM_SATA: " txt "\n"))\r
+\r
+extern EFI_COMPONENT_NAME_PROTOCOL gSataSiI3132ComponentName;\r
+extern EFI_COMPONENT_NAME2_PROTOCOL gSataSiI3132ComponentName2;\r
+\r
+/*\r
+ * Component Name Protocol Functions\r
+ */\r
+EFI_STATUS\r
+EFIAPI\r
+SataSiI3132ComponentNameGetDriverName (\r
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,\r
+ IN CHAR8 *Language,\r
+ OUT CHAR16 **DriverName\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+SataSiI3132ComponentNameGetControllerName (\r
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,\r
+ IN EFI_HANDLE ControllerHandle,\r
+ IN EFI_HANDLE ChildHandle OPTIONAL,\r
+ IN CHAR8 *Language,\r
+ OUT CHAR16 **ControllerName\r
+ );\r
+\r
+EFI_STATUS SiI3132HwResetPort (SATA_SI3132_PORT *Port);\r
+\r
+/*\r
+ * Driver Binding Protocol Functions\r
+ */\r
+EFI_STATUS\r
+EFIAPI\r
+SataSiI3132DriverBindingSupported (\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
+ IN EFI_HANDLE Controller,\r
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+SataSiI3132DriverBindingStart (\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
+ IN EFI_HANDLE Controller,\r
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+SataSiI3132DriverBindingStop (\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
+ IN EFI_HANDLE Controller,\r
+ IN UINTN NumberOfChildren,\r
+ IN EFI_HANDLE *ChildHandleBuffer\r
+ );\r
+\r
+EFI_STATUS SiI3132AtaPassThruCommand (\r
+ IN SATA_SI3132_INSTANCE *pSataSiI3132Instance,\r
+ IN SATA_SI3132_PORT *pSataPort,\r
+ IN UINT16 PortMultiplierPort,\r
+ IN OUT EFI_ATA_PASS_THRU_COMMAND_PACKET *Packet,\r
+ IN EFI_EVENT Event OPTIONAL\r
+ );\r
+\r
+/**\r
+ * EFI ATA Pass Thru Protocol\r
+ */\r
+EFI_STATUS SiI3132AtaPassThru (\r
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,\r
+ IN UINT16 Port,\r
+ IN UINT16 PortMultiplierPort,\r
+ IN OUT EFI_ATA_PASS_THRU_COMMAND_PACKET *Packet,\r
+ IN EFI_EVENT Event OPTIONAL\r
+ );\r
+\r
+EFI_STATUS SiI3132GetNextPort (\r
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,\r
+ IN OUT UINT16 *Port\r
+ );\r
+\r
+EFI_STATUS SiI3132GetNextDevice (\r
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,\r
+ IN UINT16 Port,\r
+ IN OUT UINT16 *PortMultiplierPort\r
+ );\r
+\r
+EFI_STATUS SiI3132BuildDevicePath (\r
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,\r
+ IN UINT16 Port,\r
+ IN UINT16 PortMultiplierPort,\r
+ IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath\r
+ );\r
+\r
+EFI_STATUS SiI3132GetDevice (\r
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,\r
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
+ OUT UINT16 *Port,\r
+ OUT UINT16 *PortMultiplierPort\r
+ );\r
+\r
+EFI_STATUS SiI3132ResetPort (\r
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,\r
+ IN UINT16 Port\r
+ );\r
+\r
+EFI_STATUS SiI3132ResetDevice (\r
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,\r
+ IN UINT16 Port,\r
+ IN UINT16 PortMultiplierPort\r
+ );\r
+\r
+#endif\r
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