EmbeddedPkg/MmcDxe: set I/O speed and bus width in SD stack

[mirror_edk2.git] / EmbeddedPkg / Universal / MmcDxe / Mmc.h

diff --git a/EmbeddedPkg/Universal/MmcDxe/Mmc.h b/EmbeddedPkg/Universal/MmcDxe/Mmc.h
index d570be299f955bac2df25f76b511c6581942ae21..c96ff2e12de4f8c39b58de1dc11a199b92a56a3a 100644 (file)
--- a/EmbeddedPkg/Universal/MmcDxe/Mmc.h
+++ b/EmbeddedPkg/Universal/MmcDxe/Mmc.h
@@ -1,15 +1,15 @@
 /** @file\r
   Main Header file for the MMC DXE driver\r
 \r
 /** @file\r
   Main Header file for the MMC DXE driver\r
 \r

-  Copyright (c) 2011, ARM Limited. All rights reserved.\r
-  \r
-  This program and the accompanying materials                          \r
-  are licensed and made available under the terms and conditions of the BSD License         \r
-  which accompanies this distribution.  The full text of the license may be found at        \r
-  http://opensource.org/licenses/bsd-license.php                                            \r
+  Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r

 \r
 \r

-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r

 \r
 **/\r
 \r
 \r
 **/\r
 \r


@@ -24,6 +24,8 @@
 #include <Protocol/MmcHost.h>\r
 \r
 #include <Library/UefiLib.h>\r
 #include <Protocol/MmcHost.h>\r
 \r
 #include <Library/UefiLib.h>\r

+#include <Library/DebugLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r

 \r
 #define MMC_TRACE(txt)  DEBUG((EFI_D_BLKIO, "MMC: " txt "\n"))\r
 \r
 \r
 #define MMC_TRACE(txt)  DEBUG((EFI_D_BLKIO, "MMC: " txt "\n"))\r
 \r


@@ -32,14 +34,15 @@
 \r
 #define MMC_OCR_POWERUP             0x80000000\r
 \r
 \r
 #define MMC_OCR_POWERUP             0x80000000\r
 \r

-#define MMC_CSD_GET_CCC(Response)    (Response[1] >> 20)\r
-#define MMC_CSD_GET_TRANSPEED(Response)    (Response[0] & 0xFF)\r
-#define MMC_CSD_GET_READBLLEN(Response)    ((Response[1] >> 16) & 0xF)\r
-#define MMC_CSD_GET_WRITEBLLEN(Response)  ((Response[3] >> 22) & 0xF)\r
-#define MMC_CSD_GET_FILEFORMAT(Response)  ((Response[3] >> 10) & 0x3)\r
-#define MMC_CSD_GET_FILEFORMATGRP(Response)  ((Response[3] >> 15) & 0x1)\r
-#define MMC_CSD_GET_DEVICESIZE(csd)         (((Response[2] >> 30) & 0x3) | ((Response[1] & 0x3FF) << 2))\r
-#define MMC_CSD_GET_DEVICESIZEMULT(csd)     ((Response[2] >> 15) & 0x7)\r
+#define MMC_CSD_GET_CCC(Response)    (Response[2] >> 20)\r
+#define MMC_CSD_GET_TRANSPEED(Response)    (Response[3] & 0xFF)\r
+#define MMC_CSD_GET_READBLLEN(Response)    ((Response[2] >> 16) & 0xF)\r
+#define MMC_CSD_GET_WRITEBLLEN(Response)  ((Response[0] >> 22) & 0xF)\r
+#define MMC_CSD_GET_FILEFORMAT(Response)  ((Response[0] >> 10) & 0x3)\r
+#define MMC_CSD_GET_FILEFORMATGRP(Response)  ((Response[0] >> 15) & 0x1)\r
+#define MMC_CSD_GET_DEVICESIZE(csd)         (((Response[1] >> 30) & 0x3) | ((Response[2] & 0x3FF) << 2))\r
+#define HC_MMC_CSD_GET_DEVICESIZE(Response)    ((Response[1] >> 16) | ((Response[2] & 0x40) << 16));\r
+#define MMC_CSD_GET_DEVICESIZEMULT(csd)     ((Response[1] >> 15) & 0x7)\r

 \r
 #define MMC_R0_READY_FOR_DATA               (1 << 8)\r
 \r
 \r
 #define MMC_R0_READY_FOR_DATA               (1 << 8)\r
 \r


@@ -52,25 +55,47 @@
 #define MMC_R0_STATE_TRAN       4\r
 #define MMC_R0_STATE_DATA       5\r
 \r
 #define MMC_R0_STATE_TRAN       4\r
 #define MMC_R0_STATE_DATA       5\r
 \r

+#define EMMC_CMD6_ARG_ACCESS(x)             (((x) & 0x3) << 24)\r
+#define EMMC_CMD6_ARG_INDEX(x)              (((x) & 0xFF) << 16)\r
+#define EMMC_CMD6_ARG_VALUE(x)              (((x) & 0xFF) << 8)\r
+#define EMMC_CMD6_ARG_CMD_SET(x)            (((x) & 0x7) << 0)\r
+\r

 typedef enum {\r
   UNKNOWN_CARD,\r
   MMC_CARD,              //MMC card\r
   MMC_CARD_HIGH,         //MMC Card with High capacity\r
 typedef enum {\r
   UNKNOWN_CARD,\r
   MMC_CARD,              //MMC card\r
   MMC_CARD_HIGH,         //MMC Card with High capacity\r

+  EMMC_CARD,             //eMMC 4.41 card\r

   SD_CARD,               //SD 1.1 card\r
   SD_CARD_2,             //SD 2.0 or above standard card\r
   SD_CARD_2_HIGH         //SD 2.0 or above high capacity card\r
 } CARD_TYPE;\r
 \r
 typedef struct {\r
   SD_CARD,               //SD 1.1 card\r
   SD_CARD_2,             //SD 2.0 or above standard card\r
   SD_CARD_2_HIGH         //SD 2.0 or above high capacity card\r
 } CARD_TYPE;\r
 \r
 typedef struct {\r

-  UINT32  Reserved0:   7; // 0 \r
+  UINT32  Reserved0:   7; // 0\r

   UINT32  V170_V195:   1; // 1.70V - 1.95V\r
   UINT32  V200_V260:   7; // 2.00V - 2.60V\r
   UINT32  V270_V360:   9; // 2.70V - 3.60V\r
   UINT32  RESERVED_1:  5; // Reserved\r
   UINT32  V170_V195:   1; // 1.70V - 1.95V\r
   UINT32  V200_V260:   7; // 2.00V - 2.60V\r
   UINT32  V270_V360:   9; // 2.70V - 3.60V\r
   UINT32  RESERVED_1:  5; // Reserved\r

-  UINT32  AccessMode:  2; // 00b (byte mode), 10b (sector mode) \r
-  UINT32  Busy:        1; // This bit is set to LOW if the card has not finished the power up routine\r
+  UINT32  AccessMode:  2; // 00b (byte mode), 10b (sector mode)\r
+  UINT32  PowerUp:     1; // This bit is set to LOW if the card has not finished the power up routine\r

 } OCR;\r
 \r
 } OCR;\r
 \r

+typedef struct {\r
+  UINT8   SD_SPEC:               4; // SD Memory Card - Spec. Version [59:56]\r
+  UINT8   SCR_STRUCTURE:         4; // SCR Structure [63:60]\r
+  UINT8   SD_BUS_WIDTHS:         4; // DAT Bus widths supported [51:48]\r
+  UINT8   DATA_STAT_AFTER_ERASE: 1; // Data Status after erases [55]\r
+  UINT8   SD_SECURITY:           3; // CPRM Security Support [54:52]\r
+  UINT8   EX_SECURITY_1:         1; // Extended Security Support [43]\r
+  UINT8   SD_SPEC4:              1; // Spec. Version 4.00 or higher [42]\r
+  UINT8   RESERVED_1:            2; // Reserved [41:40]\r
+  UINT8   SD_SPEC3:              1; // Spec. Version 3.00 or higher [47]\r
+  UINT8   EX_SECURITY_2:         3; // Extended Security Support [46:44]\r
+  UINT8   CMD_SUPPORT:           4; // Command Support bits [35:32]\r
+  UINT8   RESERVED_2:            4; // Reserved [39:36]\r
+  UINT32  RESERVED_3;               // Manufacturer Usage [31:0]\r
+} SCR;\r
+\r

 typedef struct {\r
   UINT32  NOT_USED;   // 1 [0:0]\r
   UINT32  CRC;        // CRC7 checksum [7:1]\r
 typedef struct {\r
   UINT32  NOT_USED;   // 1 [0:0]\r
   UINT32  CRC;        // CRC7 checksum [7:1]\r


@@ -93,14 +118,14 @@ typedef struct {
   UINT8   PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]\r
   UINT8   COPY:               1; // Copy flag (OTP) [14:14]\r
   UINT8   FILE_FORMAT_GRP:    1; // File format group [15:15]\r
   UINT8   PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]\r
   UINT8   COPY:               1; // Copy flag (OTP) [14:14]\r
   UINT8   FILE_FORMAT_GRP:    1; // File format group [15:15]\r

-  \r
+\r

   UINT16  RESERVED_2:         5; // Reserved [20:16]\r
   UINT16  WRITE_BL_PARTIAL:   1; // Partial blocks for write allowed [21:21]\r
   UINT16  WRITE_BL_LEN:       4; // Max. write data block length [25:22]\r
   UINT16  R2W_FACTOR:         3; // Write speed factor [28:26]\r
   UINT16  RESERVED_3:         2; // Reserved [30:29]\r
   UINT16  WP_GRP_ENABLE:      1; // Write protect group enable [31:31]\r
   UINT16  RESERVED_2:         5; // Reserved [20:16]\r
   UINT16  WRITE_BL_PARTIAL:   1; // Partial blocks for write allowed [21:21]\r
   UINT16  WRITE_BL_LEN:       4; // Max. write data block length [25:22]\r
   UINT16  R2W_FACTOR:         3; // Write speed factor [28:26]\r
   UINT16  RESERVED_3:         2; // Reserved [30:29]\r
   UINT16  WP_GRP_ENABLE:      1; // Write protect group enable [31:31]\r

-  \r
+\r

   UINT32  WP_GRP_SIZE:        7; // Write protect group size [38:32]\r
   UINT32  SECTOR_SIZE:        7; // Erase sector size [45:39]\r
   UINT32  ERASE_BLK_EN:       1; // Erase single block enable [46:46]\r
   UINT32  WP_GRP_SIZE:        7; // Write protect group size [38:32]\r
   UINT32  SECTOR_SIZE:        7; // Erase sector size [45:39]\r
   UINT32  ERASE_BLK_EN:       1; // Erase single block enable [46:46]\r


@@ -110,7 +135,7 @@ typedef struct {
   UINT32  VDD_R_CURR_MAX:     3; // Max. read current @ VDD max [58:56]\r
   UINT32  VDD_R_CURR_MIN:     3; // Max. read current @ VDD min [61:59]\r
   UINT32  C_SIZELow2:         2; // Device size [63:62]\r
   UINT32  VDD_R_CURR_MAX:     3; // Max. read current @ VDD max [58:56]\r
   UINT32  VDD_R_CURR_MIN:     3; // Max. read current @ VDD min [61:59]\r
   UINT32  C_SIZELow2:         2; // Device size [63:62]\r

-  \r
+\r

   UINT32  C_SIZEHigh10:       10;// Device size [73:64]\r
   UINT32  RESERVED_4:         2; // Reserved [75:74]\r
   UINT32  DSR_IMP:            1; // DSR implemented [76:76]\r
   UINT32  C_SIZEHigh10:       10;// Device size [73:64]\r
   UINT32  RESERVED_4:         2; // Reserved [75:74]\r
   UINT32  DSR_IMP:            1; // DSR implemented [76:76]\r


@@ -123,17 +148,174 @@ typedef struct {
   UINT8   TRAN_SPEED          ;  // Max. bus clock frequency [103:96]\r
   UINT8   NSAC                ;  // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]\r
   UINT8   TAAC                ;  // Data read access-time 1 [119:112]\r
   UINT8   TRAN_SPEED          ;  // Max. bus clock frequency [103:96]\r
   UINT8   NSAC                ;  // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]\r
   UINT8   TAAC                ;  // Data read access-time 1 [119:112]\r

-  \r
-  UINT8   RESERVED_5:         6; // Reserved [125:120]\r
+\r
+  UINT8   RESERVED_5:         2; // Reserved [121:120]\r
+  UINT8   SPEC_VERS:          4; // System specification version [125:122]\r

   UINT8   CSD_STRUCTURE:      2; // CSD structure [127:126]\r
 } CSD;\r
 \r
   UINT8   CSD_STRUCTURE:      2; // CSD structure [127:126]\r
 } CSD;\r
 \r

+typedef struct {\r
+  UINT8   RESERVED_1[16];                     // Reserved [15:0]\r
+  UINT8   SECURE_REMOVAL_TYPE;                // Secure Removal Type [16:16]\r
+  UINT8   PRODUCT_STATE_AWARENESS_ENABLEMENT; // Product state awareness enablement [17:17]\r
+  UINT8   MAX_PRE_LOADING_DATA_SIZE[4];       // MAX pre loading data size [21:18]\r
+  UINT8   PRE_LOADING_DATA_SIZE[4];           // Pre loading data size [25:22]\r
+  UINT8   FFU_STATUS;                         // FFU Status [26:26]\r
+  UINT8   RESERVED_2[2];                      // Reserved [28:27]\r
+  UINT8   MODE_OPERATION_CODES;               // Mode operation codes [29:29]\r
+  UINT8   MODE_CONFIG;                        // Mode config [30:30]\r
+  UINT8   RESERVED_3;                         // Reserved [31:31]\r
+  UINT8   FLUSH_CACHE;                        // Flushing of the cache [32:32]\r
+  UINT8   CACHE_CTRL;                         // Control to turn the cache ON/OFF [33:33]\r
+  UINT8   POWER_OFF_NOTIFICATION;             // Power Off Notification [34:34]\r
+  UINT8   PACKED_FAILURE_INDEX;               // Packed command failure index [35:35]\r
+  UINT8   PACKED_COMMAND_STATUS;              // Packed command status [36:36]\r
+  UINT8   CONTEXT_CONF[15];                   // Context configuration [51:37]\r
+  UINT8   EXT_PARTITIONS_ATTRIBUTE[2];        // Extended partitions attribute [53:52]\r
+  UINT8   EXCEPTION_EVENTS_STATUS[2];         // Exception events status [55:54]\r
+  UINT8   EXCEPTION_EVENTS_CTRL[2];           // Exception events control [57:56]\r
+  UINT8   DYNCAP_NEEDED;                      // Number of addressed group to be released [58:58]\r
+  UINT8   CLASS_6_CTRL;                       // Class 6 commands control [59:59]\r
+  UINT8   INI_TIMEOUT_EMU;                    // 1st initialization after disabling sector size emulation [60:60]\r
+  UINT8   DATA_SECTOR_SIZE;                   // Sector size [61:61]\r
+  UINT8   USE_NATIVE_SECTOR;                  // Sector size emulation [62:62]\r
+  UINT8   NATIVE_SECTOR_SIZE;                 // Native sector size [63:63]\r
+  UINT8   VENDOR_SPECIFIC_FIELD[64];          // Vendor specific fields [127:64]\r
+  UINT8   RESERVED_4[2];                      // Reserved [129:128]\r
+  UINT8   PROGRAM_CID_CSD_DDR_SUPPORT;        // Program CID/CSD in DDR mode support [130:130]\r
+  UINT8   PERIODIC_WAKEUP;                    // Periodic wake-up [131:131]\r
+  UINT8   TCASE_SUPPORT;                      // Package case temperature is controlled [132:132]\r
+  UINT8   PRODUCTION_STATE_AWARENESS;         // Production state awareness [133:133]\r
+  UINT8   SECTOR_BAD_BLK_MGMNT;               // Bad block management mode [134:134]\r
+  UINT8   RESERVED_5;                         // Reserved [135:135]\r
+  UINT8   ENH_START_ADDR[4];                  // Enhanced user data start address [139:136]\r
+  UINT8   ENH_SIZE_MULT[3];                   // Enhanced user data area size [142:140]\r
+  UINT8   GP_SIZE_MULT[12];                   // General purpose partition size [154:143]\r
+  UINT8   PARTITION_SETTING_COMPLETED;        // Partitioning setting [155:155]\r
+  UINT8   PARTITIONS_ATTRIBUTE;               // Partitions attribute [156:156]\r
+  UINT8   MAX_ENH_SIZE_MULT[3];               // Max enhanced area size [159:157]\r
+  UINT8   PARTITIONING_SUPPORT;               // Partitioning [160:160]\r
+  UINT8   HPI_MGMT;                           // HPI management [161:161]\r
+  UINT8   RST_N_FUNCTION;                     // H/W reset function [162:162]\r
+  UINT8   BKOPS_EN;                           // Enable background operations handshake [163:163]\r
+  UINT8   BKOPS_START;                        // Manually start background operations [164:164]\r
+  UINT8   SANITIZE_START;                     // Start sanitize operation [165:165]\r
+  UINT8   WR_REL_PARAM;                       // Write reliability parameter register [166:166]\r
+  UINT8   WR_REL_SET;                         // Write reliability setting register [167:167]\r
+  UINT8   RPMB_SIZE_MULT;                     // RPMB size [168:168]\r
+  UINT8   FW_CONFIG;                          // FW configuration [169:169]\r
+  UINT8   RESERVED_6;                         // Reserved [170:170]\r
+  UINT8   USER_WP;                            // User area write protection register [171:171]\r
+  UINT8   RESERVED_7;                         // Reserved [172:172]\r
+  UINT8   BOOT_WP;                            // Boot area write protection register [173:173]\r
+  UINT8   BOOT_WP_STATUS;                     // Boot write protection register [174:174]\r
+  UINT8   ERASE_GROUP_DEF;                    // High-density erase group definition [175:175]\r
+  UINT8   RESERVED_8;                         // Reserved [176:176]\r
+  UINT8   BOOT_BUS_CONDITIONS;                // Boot bus conditions [177:177]\r
+  UINT8   BOOT_CONFIG_PROT;                   // Boot config protection [178:178]\r
+  UINT8   PARTITION_CONFIG;                   // Partition config [179:179]\r
+  UINT8   RESERVED_9;                         // Reserved [180:180]\r
+  UINT8   ERASED_MEM_CONT;                    // Erased memory content [181:181]\r
+  UINT8   RESERVED_10;                        // Reserved [182:182]\r
+  UINT8   BUS_WIDTH;                          // Bus width mode [183:183]\r
+  UINT8   RESERVED_11;                        // Reserved [184:184]\r
+  UINT8   HS_TIMING;                          // High-speed interface timing [185:185]\r
+  UINT8   RESERVED_12;                        // Reserved [186:186]\r
+  UINT8   POWER_CLASS;                        // Power class [187:187]\r
+  UINT8   RESERVED_13;                        // Reserved [188:188]\r
+  UINT8   CMD_SET_REV;                        // Command set revision [189:189]\r
+  UINT8   RESERVED_14;                        // Reserved [190:190]\r
+  UINT8   CMD_SET;                            // Command set [191:191]\r
+  UINT8   EXT_CSD_REV;                        // Extended CSD revision [192:192]\r
+  UINT8   RESERVED_15;                        // Reserved [193:193]\r
+  UINT8   CSD_STRUCTURE;                      // CSD Structure [194:194]\r
+  UINT8   RESERVED_16;                        // Reserved [195:195]\r
+  UINT8   DEVICE_TYPE;                        // Device type [196:196]\r
+  UINT8   DRIVER_STRENGTH;                    // I/O Driver strength [197:197]\r
+  UINT8   OUT_OF_INTERRUPT_TIME;              // Out-of-interrupt busy timing [198:198]\r
+  UINT8   PARTITION_SWITCH_TIME;              // Partition switching timing [199:199]\r
+  UINT8   PWR_CL_52_195;                      // Power class for 52MHz at 1.95V 1 R [200:200]\r
+  UINT8   PWR_CL_26_195;                      // Power class for 26MHz at 1.95V 1 R [201:201]\r
+  UINT8   PWR_CL_52_360;                      // Power class for 52MHz at 3.6V 1 R [202:202]\r
+  UINT8   PWR_CL_26_360;                      // Power class for 26MHz at 3.6V 1 R [203:203]\r
+  UINT8   RESERVED_17;                        // Reserved [204:204]\r
+  UINT8   MIN_PERF_R_4_26;                    // Minimum read performance for 4bit at 26MHz [205:205]\r
+  UINT8   MIN_PERF_W_4_26;                    // Minimum write performance for 4bit at 26MHz [206:206]\r
+  UINT8   MIN_PERF_R_8_26_4_52;               // Minimum read performance for 8bit at 26MHz, for 4bit at 52MHz [207:207]\r
+  UINT8   MIN_PERF_W_8_26_4_52;               // Minimum write performance for 8bit at 26MHz, for 4bit at 52MHz [208:208]\r
+  UINT8   MIN_PERF_R_8_52;                    // Minimum read performance for 8bit at 52MHz [209:209]\r
+  UINT8   MIN_PERF_W_8_52;                    // Minimum write performance for 8bit at 52MHz [210:210]\r
+  UINT8   RESERVED_18;                        // Reserved [211:211]\r
+  UINT32  SECTOR_COUNT;                       // Sector count [215:212]\r
+  UINT8   SLEEP_NOTIFICATION_TIME;            // Sleep notification timout [216:216]\r
+  UINT8   S_A_TIMEOUT;                        // Sleep/awake timeout [217:217]\r
+  UINT8   PRODUCTION_STATE_AWARENESS_TIMEOUT; // Production state awareness timeout [218:218]\r
+  UINT8   S_C_VCCQ;                           // Sleep current (VCCQ) [219:219]\r
+  UINT8   S_C_VCC;                            // Sleep current (VCC) [220:220]\r
+  UINT8   HC_WP_GRP_SIZE;                     // High-capacity write protect group size [221:221]\r
+  UINT8   REL_WR_SECTOR_C;                    // Reliable write sector count [222:222]\r
+  UINT8   ERASE_TIMEOUT_MULT;                 // High-capacity erase timeout [223:223]\r
+  UINT8   HC_ERASE_GRP_SIZE;                  // High-capacity erase unit size [224:224]\r
+  UINT8   ACC_SIZE;                           // Access size [225:225]\r
+  UINT8   BOOT_SIZE_MULTI;                    // Boot partition size [226:226]\r
+  UINT8   RESERVED_19;                        // Reserved [227:227]\r
+  UINT8   BOOT_INFO;                          // Boot information [228:228]\r
+  UINT8   SECURE_TRIM_MULT;                   // Secure TRIM Multiplier [229:229]\r
+  UINT8   SECURE_ERASE_MULT;                  // Secure Erase Multiplier [230:230]\r
+  UINT8   SECURE_FEATURE_SUPPORT;             // Secure Feature Support [231:231]\r
+  UINT8   TRIM_MULT;                          // TRIM Multiplier [232:232]\r
+  UINT8   RESERVED_20;                        // Reserved [233:233]\r
+  UINT8   MIN_PREF_DDR_R_8_52;                // Minimum read performance for 8bit at 52MHz in DDR mode [234:234]\r
+  UINT8   MIN_PREF_DDR_W_8_52;                // Minimum write performance for 8bit at 52MHz in DDR mode [235:235]\r
+  UINT8   PWR_CL_200_130;                     // Power class for 200MHz at VCCQ=1.3V, VCC=3.6V [236:236]\r
+  UINT8   PWR_CL_200_195;                     // Power class for 200MHz at VCCQ=1.95V, VCC=3.6V [237:237]\r
+  UINT8   PWR_CL_DDR_52_195;                  // Power class for 52MHz, DDR at 1.95V [238:238]\r
+  UINT8   PWR_CL_DDR_52_360;                  // Power class for 52Mhz, DDR at 3.6V [239:239]\r
+  UINT8   RESERVED_21;                        // Reserved [240:240]\r
+  UINT8   INI_TIMEOUT_AP;                     // 1st initialization time after partitioning [241:241]\r
+  UINT8   CORRECTLY_PRG_SECTORS_NUM[4];       // Number of correctly programmed sectors [245:242]\r
+  UINT8   BKOPS_STATUS;                       // Background operations status [246:246]\r
+  UINT8   POWER_OFF_LONG_TIME;                // Power off notification (long) timeout [247:247]\r
+  UINT8   GENERIC_CMD6_TIME;                  // Generic CMD6 timeout [248:248]\r
+  UINT8   CACHE_SIZE[4];                      // Cache size [252:249]\r
+  UINT8   PWR_CL_DDR_200_360;                 // Power class for 200MHz, DDR at VCC=3.6V [253:253]\r
+  UINT8   FIRMWARE_VERSION[8];                // Firmware version [261:254]\r
+  UINT8   DEVICE_VERSION[2];                  // Device version [263:262]\r
+  UINT8   OPTIMAL_TRIM_UNIT_SIZE;             // Optimal trim unit size [264:264]\r
+  UINT8   OPTIMAL_WRITE_SIZE;                 // Optimal write size [265:265]\r
+  UINT8   OPTIMAL_READ_SIZE;                  // Optimal read size [266:266]\r
+  UINT8   PRE_EOL_INFO;                       // Pre EOL information [267:267]\r
+  UINT8   DEVICE_LIFE_TIME_EST_TYP_A;         // Device life time estimation type A [268:268]\r
+  UINT8   DEVICE_LIFE_TIME_EST_TYP_B;         // Device life time estimation type B [269:269]\r
+  UINT8   VENDOR_PROPRIETARY_HEALTH_REPORT[32];         // Vendor proprietary health report [301:270]\r
+  UINT8   NUMBER_OF_FW_SECTORS_CORRECTLY_PROGRAMMED[4]; // Number of FW sectors correctly programmed [305:302]\r
+  UINT8   RESERVED_22[181];                   // Reserved [486:306]\r
+  UINT8   FFU_ARG[4];                         // FFU argument [490:487]\r
+  UINT8   OPERATION_CODE_TIMEOUT;             // Operation codes timeout [491:491]\r
+  UINT8   FFU_FEATURES;                       // FFU features [492:492]\r
+  UINT8   SUPPORTED_MODES;                    // Supported modes [493:493]\r
+  UINT8   EXT_SUPPORT;                        // Extended partitions attribute support [494:494]\r
+  UINT8   LARGE_UNIT_SIZE_M1;                 // Large unit size [495:495]\r
+  UINT8   CONTEXT_CAPABILITIES;               // Context management capabilities [496:496]\r
+  UINT8   TAG_RES_SIZE;                       // Tag resource size [497:497]\r
+  UINT8   TAG_UNIT_SIZE;                      // Tag unit size [498:498]\r
+  UINT8   DATA_TAG_SUPPORT;                   // Data tag support [499:499]\r
+  UINT8   MAX_PACKED_WRITES;                  // Max packed write commands [500:500]\r
+  UINT8   MAX_PACKED_READS;                   // Max packed read commands [501:501]\r
+  UINT8   BKOPS_SUPPORT;                      // Background operations support [502:502]\r
+  UINT8   HPI_FEATURES;                       // HPI features [503:503]\r
+  UINT8   S_CMD_SET;                          // Supported command sets [504:504]\r
+  UINT8   EXT_SECURITY_ERR;                   // Extended security commands error [505:505]\r
+  UINT8   RESERVED_23[6];                     // Reserved [511:506]\r
+} ECSD;\r
+\r

 typedef struct  {\r
   UINT16    RCA;\r
   CARD_TYPE CardType;\r
   OCR       OCRData;\r
   CID       CIDData;\r
   CSD       CSDData;\r
 typedef struct  {\r
   UINT16    RCA;\r
   CARD_TYPE CardType;\r
   OCR       OCRData;\r
   CID       CIDData;\r
   CSD       CSDData;\r

+  ECSD      ECSDData;                         // MMC V4 extended card specific\r

 } CARD_INFO;\r
 \r
 typedef struct _MMC_HOST_INSTANCE {\r
 } CARD_INFO;\r
 \r
 typedef struct _MMC_HOST_INSTANCE {\r


@@ -146,7 +328,7 @@ typedef struct _MMC_HOST_INSTANCE {
   EFI_BLOCK_IO_PROTOCOL     BlockIo;\r
   CARD_INFO                 CardInfo;\r
   EFI_MMC_HOST_PROTOCOL     *MmcHost;\r
   EFI_BLOCK_IO_PROTOCOL     BlockIo;\r
   CARD_INFO                 CardInfo;\r
   EFI_MMC_HOST_PROTOCOL     *MmcHost;\r

-  \r
+\r

   BOOLEAN                   Initialized;\r
 } MMC_HOST_INSTANCE;\r
 \r
   BOOLEAN                   Initialized;\r
 } MMC_HOST_INSTANCE;\r
 \r


@@ -183,7 +365,7 @@ extern LIST_ENTRY mMmcHostPool;
 /**\r
   Reset the block device.\r
 \r
 /**\r
   Reset the block device.\r
 \r

-  This function implements EFI_BLOCK_IO_PROTOCOL.Reset(). \r
+  This function implements EFI_BLOCK_IO_PROTOCOL.Reset().\r

   It resets the block device hardware.\r
   ExtendedVerification is ignored in this implementation.\r
 \r
   It resets the block device hardware.\r
   ExtendedVerification is ignored in this implementation.\r
 \r


@@ -205,7 +387,7 @@ MmcReset (
 /**\r
   Reads the requested number of blocks from the device.\r
 \r
 /**\r
   Reads the requested number of blocks from the device.\r
 \r

-  This function implements EFI_BLOCK_IO_PROTOCOL.ReadBlocks(). \r
+  This function implements EFI_BLOCK_IO_PROTOCOL.ReadBlocks().\r

   It reads the requested number of blocks from the device.\r
   All the blocks are read, or an error is returned.\r
 \r
   It reads the requested number of blocks from the device.\r
   All the blocks are read, or an error is returned.\r
 \r


@@ -239,7 +421,7 @@ MmcReadBlocks (
 /**\r
   Writes a specified number of blocks to the device.\r
 \r
 /**\r
   Writes a specified number of blocks to the device.\r
 \r

-  This function implements EFI_BLOCK_IO_PROTOCOL.WriteBlocks(). \r
+  This function implements EFI_BLOCK_IO_PROTOCOL.WriteBlocks().\r

   It writes a specified number of blocks to the device.\r
   All blocks are written, or an error is returned.\r
 \r
   It writes a specified number of blocks to the device.\r
   All blocks are written, or an error is returned.\r
 \r


@@ -287,4 +469,47 @@ MmcFlushBlocks (
   IN EFI_BLOCK_IO_PROTOCOL  *This\r
   );\r
 \r
   IN EFI_BLOCK_IO_PROTOCOL  *This\r
   );\r
 \r

+EFI_STATUS\r
+MmcNotifyState (\r
+  IN MMC_HOST_INSTANCE      *MmcHostInstance,\r
+  IN MMC_STATE               State\r
+  );\r
+\r
+EFI_STATUS\r
+InitializeMmcDevice (\r
+  IN  MMC_HOST_INSTANCE     *MmcHost\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+CheckCardsCallback (\r
+  IN  EFI_EVENT   Event,\r
+  IN  VOID        *Context\r
+  );\r
+\r
+VOID\r
+PrintCSD (\r
+  IN UINT32* Csd\r
+  );\r
+\r
+VOID\r
+PrintRCA (\r
+  IN UINT32 Rca\r
+  );\r
+\r
+VOID\r
+PrintOCR (\r
+  IN UINT32 Ocr\r
+  );\r
+\r
+VOID\r
+PrintResponseR1 (\r
+  IN  UINT32 Response\r
+  );\r
+\r
+VOID\r
+PrintCID (\r
+  IN UINT32* Cid\r
+  );\r
+\r

 #endif\r
 #endif\r