/** @file\r
+ PCI eunmeration implementation on entire PCI bus system for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2008, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2006 - 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
\r
-**/\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
+**/\r
\r
#include "PciBus.h"\r
-#include "PciEnumerator.h"\r
-#include "PciResourceSupport.h"\r
-#include "PciOptionRomSupport.h"\r
\r
/**\r
This routine is used to enumerate entire pci bus system\r
in a given platform.\r
\r
@param Controller Parent controller handle.\r
- \r
- @return Status of enumerating.\r
+\r
+ @retval EFI_SUCCESS PCI enumeration finished successfully.\r
+ @retval other Some error occurred when enumerating the pci bus system.\r
+\r
**/\r
EFI_STATUS\r
PciEnumerator (\r
}\r
\r
/**\r
- Enumerate PCI root bridge\r
- \r
+ Enumerate PCI root bridge.\r
+\r
@param PciResAlloc Pointer to protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
@param RootBridgeDev Instance of root bridge device.\r
- \r
- @retval EFI_SUCCESS Success to enumerate root bridge.\r
- @retval Others Fail to enumerate root bridge.\r
- \r
+\r
+ @retval EFI_SUCCESS Successfully enumerated root bridge.\r
+ @retval other Failed to enumerate root bridge.\r
+\r
**/\r
EFI_STATUS\r
PciRootBridgeEnumerator (\r
)\r
{\r
EFI_STATUS Status;\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *pConfiguration;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;\r
UINT8 SubBusNumber;\r
UINT8 StartBusNumber;\r
UINT8 PaddedBusRange;\r
Status = PciResAlloc->StartBusEnumeration (\r
PciResAlloc,\r
RootBridgeHandle,\r
- (VOID **) &pConfiguration\r
+ (VOID **) &Configuration\r
);\r
\r
if (EFI_ERROR (Status)) {\r
//\r
// Get the bus number to start with\r
//\r
- StartBusNumber = (UINT8) (pConfiguration->AddrRangeMin);\r
- PaddedBusRange = (UINT8) (pConfiguration->AddrRangeMax);\r
+ StartBusNumber = (UINT8) (Configuration->AddrRangeMin);\r
+ PaddedBusRange = (UINT8) (Configuration->AddrRangeMax);\r
\r
//\r
// Initialize the subordinate bus number\r
// Reset all assigned PCI bus number\r
//\r
ResetAllPpbBusNumber (\r
- RootBridgeDev, \r
+ RootBridgeDev,\r
StartBusNumber\r
);\r
\r
//\r
Status = PciScanBus (\r
RootBridgeDev,\r
- (UINT8) (pConfiguration->AddrRangeMin),\r
+ (UINT8) (Configuration->AddrRangeMin),\r
&SubBusNumber,\r
&PaddedBusRange\r
);\r
//\r
// Assign max bus number scanned\r
//\r
- pConfiguration->AddrLen = SubBusNumber - StartBusNumber + 1 + PaddedBusRange;\r
+ Configuration->AddrLen = SubBusNumber - StartBusNumber + 1 + PaddedBusRange;\r
\r
//\r
// Set bus number\r
Status = PciResAlloc->SetBusNumbers (\r
PciResAlloc,\r
RootBridgeHandle,\r
- pConfiguration\r
+ Configuration\r
);\r
- \r
- gBS->FreePool (pConfiguration);\r
- \r
+\r
+ FreePool (Configuration);\r
+\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
}\r
\r
/**\r
- This routine is used to process option rom on a certain root bridge\r
- \r
- @param Bridge Given parent's root bridge\r
- @param RomBase Base address of ROM driver loaded from\r
- @param MaxLength Max rom size\r
- \r
- @retval EFI_SUCCESS Success to process option rom image.\r
+ This routine is used to process all PCI devices' Option Rom\r
+ on a certain root bridge.\r
+\r
+ @param Bridge Given parent's root bridge.\r
+ @param RomBase Base address of ROM driver loaded from.\r
+ @param MaxLength Maximum rom size.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
ProcessOptionRom (\r
IN PCI_IO_DEVICE *Bridge,\r
IN UINT64 RomBase,\r
\r
CurrentLink = CurrentLink->ForwardLink;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
This routine is used to assign bus number to the given PCI bus system\r
- \r
- @param Bridge Parent root bridge instance.\r
- @param StartBusNumber Number of beginning.\r
- @param SubBusNumber the number of sub bus.\r
- \r
- @retval EFI_SUCCESS Success to assign bus number.\r
+\r
+ @param Bridge Parent root bridge instance.\r
+ @param StartBusNumber Number of beginning.\r
+ @param SubBusNumber The number of sub bus.\r
+\r
+ @retval EFI_SUCCESS Successfully assigned bus number.\r
+ @retval EFI_DEVICE_ERROR Failed to assign bus number.\r
+\r
**/\r
EFI_STATUS\r
PciAssignBusNumber (\r
//\r
// Check to see whether a pci device is present\r
//\r
-\r
Status = PciDevicePresent (\r
PciRootBridgeIo,\r
&Pci,\r
\r
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);\r
\r
- Status = PciRootBridgeIoWrite (\r
+ Status = PciRootBridgeIo->Pci.Write (\r
PciRootBridgeIo,\r
- &Pci,\r
EfiPciWidthUint16,\r
Address,\r
1,\r
// Initialize SubBusNumber to SecondBus\r
//\r
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);\r
- Status = PciRootBridgeIoWrite (\r
+ Status = PciRootBridgeIo->Pci.Write (\r
PciRootBridgeIo,\r
- &Pci,\r
EfiPciWidthUint8,\r
Address,\r
1,\r
if (IS_PCI_BRIDGE (&Pci)) {\r
\r
Register8 = 0xFF;\r
- Status = PciRootBridgeIoWrite (\r
+ Status = PciRootBridgeIo->Pci.Write (\r
PciRootBridgeIo,\r
- &Pci,\r
EfiPciWidthUint8,\r
Address,\r
1,\r
//\r
// Set the current maximum bus number under the PPB\r
//\r
-\r
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);\r
\r
- Status = PciRootBridgeIoWrite (\r
+ Status = PciRootBridgeIo->Pci.Write (\r
PciRootBridgeIo,\r
- &Pci,\r
EfiPciWidthUint8,\r
Address,\r
1,\r
//\r
// Skip sub functions, this is not a multi function device\r
//\r
-\r
Func = PCI_MAX_FUNC;\r
}\r
}\r
\r
@param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
@param RootBridgeDev Root bridge instance\r
- \r
- @retval EFI_SUCCESS Success to get root bridge's attribute\r
- @retval Others Fail to get attribute\r
+\r
+ @retval EFI_SUCCESS Successfully got root bridge's attribute.\r
+ @retval other Failed to get attribute.\r
+\r
**/\r
EFI_STATUS\r
DetermineRootBridgeAttributes (\r
// Here is the point where PCI bus driver calls HOST bridge allocation protocol\r
// Currently we hardcoded for ea815\r
//\r
-\r
if ((Attributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0) {\r
RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED;\r
}\r
}\r
\r
/**\r
- Get Max Option Rom size on this bridge\r
- \r
- @param Bridge Bridge device instance.\r
- @return Max size of option rom.\r
+ Get Max Option Rom size on specified bridge.\r
+\r
+ @param Bridge Given bridge device instance.\r
+\r
+ @return Max size of option rom needed.\r
+\r
**/\r
UINT64\r
GetMaxOptionRomSize (\r
\r
/**\r
Process attributes of devices on this host bridge\r
- \r
+\r
@param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
- \r
+\r
+ @retval EFI_SUCCESS Successfully process attribute.\r
@retval EFI_NOT_FOUND Can not find the specific root bridge device.\r
- @retval EFI_SUCCESS Success Process attribute.\r
- @retval Others Can not determine the root bridge device's attribute.\r
+ @retval other Failed to determine the root bridge device's attribute.\r
+\r
**/\r
EFI_STATUS\r
PciHostBridgeDeviceAttribute (\r
}\r
\r
/**\r
- Get resource allocation status from the ACPI pointer\r
-\r
- @param AcpiConfig Point to Acpi configuration table\r
- @param IoResStatus Return the status of I/O resource\r
- @param Mem32ResStatus Return the status of 32-bit Memory resource\r
- @param PMem32ResStatus Return the status of 32-bit PMemory resource\r
- @param Mem64ResStatus Return the status of 64-bit Memory resource\r
- @param PMem64ResStatus Return the status of 64-bit PMemory resource\r
- \r
- @retval EFI_SUCCESS Success to get resource allocation status from ACPI configuration table.\r
+ Get resource allocation status from the ACPI resource descriptor.\r
+\r
+ @param AcpiConfig Point to Acpi configuration table.\r
+ @param IoResStatus Return the status of I/O resource.\r
+ @param Mem32ResStatus Return the status of 32-bit Memory resource.\r
+ @param PMem32ResStatus Return the status of 32-bit Prefetchable Memory resource.\r
+ @param Mem64ResStatus Return the status of 64-bit Memory resource.\r
+ @param PMem64ResStatus Return the status of 64-bit Prefetchable Memory resource.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
GetResourceAllocationStatus (\r
VOID *AcpiConfig,\r
OUT UINT64 *IoResStatus,\r
OUT UINT64 *PMem64ResStatus\r
)\r
{\r
-\r
UINT8 *Temp;\r
UINT64 ResStatus;\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ptr;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ACPIAddressDesc;\r
\r
Temp = (UINT8 *) AcpiConfig;\r
\r
while (*Temp == ACPI_ADDRESS_SPACE_DESCRIPTOR) {\r
\r
- ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp;\r
- ResStatus = ptr->AddrTranslationOffset;\r
+ ACPIAddressDesc = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp;\r
+ ResStatus = ACPIAddressDesc->AddrTranslationOffset;\r
\r
- switch (ptr->ResType) {\r
+ switch (ACPIAddressDesc->ResType) {\r
case 0:\r
- if (ptr->AddrSpaceGranularity == 32) {\r
- if (ptr->SpecificFlag == 0x06) {\r
+ if (ACPIAddressDesc->AddrSpaceGranularity == 32) {\r
+ if (ACPIAddressDesc->SpecificFlag == 0x06) {\r
//\r
// Pmem32\r
//\r
}\r
}\r
\r
- if (ptr->AddrSpaceGranularity == 64) {\r
- if (ptr->SpecificFlag == 0x06) {\r
+ if (ACPIAddressDesc->AddrSpaceGranularity == 64) {\r
+ if (ACPIAddressDesc->SpecificFlag == 0x06) {\r
//\r
// PMem64\r
//\r
\r
Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
- Remove a PCI device from device pool and mark its bar\r
- \r
+ Remove a PCI device from device pool and mark its bar.\r
+\r
@param PciDevice Instance of Pci device.\r
- \r
- @retval EFI_SUCCESS Success Operation.\r
- @retval EFI_ABORTED Pci device is a root bridge.\r
+\r
+ @retval EFI_SUCCESS Successfully remove the PCI device.\r
+ @retval EFI_ABORTED Pci device is a root bridge or a PCI-PCI bridge.\r
+\r
**/\r
EFI_STATUS\r
RejectPciDevice (\r
//\r
// Remove the padding resource from a bridge\r
//\r
- if ( IS_PCI_BRIDGE(&PciDevice->Pci) && \\r
+ if ( IS_PCI_BRIDGE(&PciDevice->Pci) &&\r
PciDevice->ResourcePaddingDescriptors != NULL ) {\r
- gBS->FreePool (PciDevice->ResourcePaddingDescriptors);\r
+ FreePool (PciDevice->ResourcePaddingDescriptors);\r
PciDevice->ResourcePaddingDescriptors = NULL;\r
return EFI_SUCCESS;\r
}\r
\r
/**\r
Determine whethter a PCI device can be rejected.\r
- \r
- @param PciResNode Pointer to Pci resource node instance.\r
- \r
- @return whethter a PCI device can be rejected.\r
+\r
+ @param PciResNode Pointer to Pci resource node instance.\r
+\r
+ @retval TRUE The PCI device can be rejected.\r
+ @retval TRUE The PCI device cannot be rejected.\r
+\r
**/\r
BOOLEAN\r
IsRejectiveDevice (\r
}\r
\r
/**\r
- Compare two resource node and get the larger resource consumer\r
- \r
+ Compare two resource nodes and get the larger resource consumer.\r
+\r
@param PciResNode1 resource node 1 want to be compared\r
@param PciResNode2 resource node 2 want to be compared\r
- \r
- @return Larger resource consumer.\r
+\r
+ @return Larger resource node.\r
+\r
**/\r
PCI_RESOURCE_NODE *\r
GetLargerConsumerDevice (\r
}\r
\r
return PciResNode2;\r
-\r
}\r
\r
\r
/**\r
Get the max resource consumer in the host resource pool.\r
- \r
+\r
@param ResPool Pointer to resource pool node.\r
- \r
- @return the max resource consumer in the host resource pool.\r
+\r
+ @return The max resource consumer in the host resource pool.\r
+\r
**/\r
PCI_RESOURCE_NODE *\r
GetMaxResourceConsumerDevice (\r
\r
/**\r
Adjust host bridge allocation so as to reduce resource requirement\r
- \r
+\r
@param IoPool Pointer to instance of I/O resource Node.\r
@param Mem32Pool Pointer to instance of 32-bit memory resource Node.\r
- @param PMem32Pool Pointer to instance of 32-bit Pmemory resource node.\r
+ @param PMem32Pool Pointer to instance of 32-bit Prefetchable memory resource node.\r
@param Mem64Pool Pointer to instance of 64-bit memory resource node.\r
- @param PMem64Pool Pointer to instance of 64-bit Pmemory resource node.\r
+ @param PMem64Pool Pointer to instance of 64-bit Prefetchable memory resource node.\r
@param IoResStatus Status of I/O resource Node.\r
@param Mem32ResStatus Status of 32-bit memory resource Node.\r
- @param PMem32ResStatus Status of 32-bit Pmemory resource node.\r
+ @param PMem32ResStatus Status of 32-bit Prefetchable memory resource node.\r
@param Mem64ResStatus Status of 64-bit memory resource node.\r
- @param PMem64ResStatus Status of 64-bit Pmemory resource node.\r
+ @param PMem64ResStatus Status of 64-bit Prefetchable memory resource node.\r
+\r
+ @retval EFI_SUCCESS Successfully adjusted resoruce on host bridge.\r
+ @retval EFI_ABORTED Host bridge hasn't this resource type or no resource be adjusted.\r
+\r
**/\r
EFI_STATUS\r
PciHostBridgeAdjustAllocation (\r
continue;\r
}\r
\r
- if (ResStatus[ResType] == EFI_RESOURCE_NONEXISTENT) {\r
+ if (ResStatus[ResType] == EFI_RESOURCE_NOT_SATISFIED) {\r
//\r
- // Hostbridge hasn't this resource type\r
+ // Host bridge hasn't this resource type\r
//\r
return EFI_ABORTED;\r
}\r
/**\r
Summary requests for all resource type, and contruct ACPI resource\r
requestor instance.\r
- \r
+\r
@param Bridge detecting bridge\r
@param IoNode Pointer to instance of I/O resource Node\r
@param Mem32Node Pointer to instance of 32-bit memory resource Node\r
@param PMem32Node Pointer to instance of 32-bit Pmemory resource node\r
@param Mem64Node Pointer to instance of 64-bit memory resource node\r
@param PMem64Node Pointer to instance of 64-bit Pmemory resource node\r
- @param pConfig outof buffer holding new constructed APCI resource requestor\r
+ @param Config Output buffer holding new constructed APCI resource requestor\r
+\r
+ @retval EFI_SUCCESS Successfully constructed ACPI resource.\r
+ @retval EFI_OUT_OF_RESOURCES No memory availabe.\r
+\r
**/\r
EFI_STATUS\r
ConstructAcpiResourceRequestor (\r
IN PCI_RESOURCE_NODE *PMem32Node,\r
IN PCI_RESOURCE_NODE *Mem64Node,\r
IN PCI_RESOURCE_NODE *PMem64Node,\r
- OUT VOID **pConfig\r
+ OUT VOID **Config\r
)\r
{\r
UINT8 NumConfig;\r
NumConfig = 0;\r
Aperture = 0;\r
\r
- *pConfig = NULL;\r
+ *Config = NULL;\r
\r
//\r
// if there is io request, add to the io aperture\r
// If there is at least one type of resource request,\r
// allocate a acpi resource node\r
//\r
- Configuration = AllocatePool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
+ Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
if (Configuration == NULL) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
\r
- ZeroMem (\r
- Configuration,\r
- sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)\r
- );\r
-\r
Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;\r
\r
//\r
Ptr->AddrLen = IoNode->Length;\r
Ptr->AddrRangeMax = IoNode->Alignment;\r
\r
- Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) ((UINT8 *) Ptr + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR));\r
+ Ptr++;\r
}\r
//\r
// Deal with mem32 aperture\r
Ptr->AddrLen = Mem32Node->Length;\r
Ptr->AddrRangeMax = Mem32Node->Alignment;\r
\r
- Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) ((UINT8 *) Ptr + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR));\r
+ Ptr++;\r
}\r
\r
//\r
Ptr->AddrLen = PMem32Node->Length;\r
Ptr->AddrRangeMax = PMem32Node->Alignment;\r
\r
- Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) ((UINT8 *) Ptr + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR));\r
+ Ptr++;\r
}\r
//\r
// Deal with mem64 aperture\r
Ptr->AddrLen = Mem64Node->Length;\r
Ptr->AddrRangeMax = Mem64Node->Alignment;\r
\r
- Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) ((UINT8 *) Ptr + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR));\r
+ Ptr++;\r
}\r
//\r
// Deal with Pmem64 aperture\r
Ptr->AddrLen = PMem64Node->Length;\r
Ptr->AddrRangeMax = PMem64Node->Alignment;\r
\r
- Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) ((UINT8 *) Ptr + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR));\r
+ Ptr++;\r
}\r
\r
//\r
// put the checksum\r
//\r
- PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) ((UINT8 *) Ptr);\r
+ PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) Ptr;\r
\r
PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;\r
PtrEnd->Checksum = 0;\r
//\r
// If there is no resource request\r
//\r
- Configuration = AllocatePool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
+ Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
if (Configuration == NULL) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
\r
- ZeroMem (Configuration, sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
-\r
Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) (Configuration);\r
Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
\r
- PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) (Configuration + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR));\r
+ PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) (Ptr + 1);\r
PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;\r
PtrEnd->Checksum = 0;\r
}\r
\r
- *pConfig = Configuration;\r
+ *Config = Configuration;\r
\r
return EFI_SUCCESS;\r
}\r
\r
/**\r
- Get resource base from a acpi configuration descriptor.\r
- \r
- @param pConfig an acpi configuration descriptor.\r
- @param IoBase output of I/O resource base address.\r
- @param Mem32Base output of 32-bit memory base address.\r
- @param PMem32Base output of 32-bit pmemory base address.\r
- @param Mem64Base output of 64-bit memory base address.\r
- @param PMem64Base output of 64-bit pmemory base address.\r
- \r
- @return EFI_SUCCESS Success operation.\r
+ Get resource base from an acpi configuration descriptor.\r
+\r
+ @param Config An acpi configuration descriptor.\r
+ @param IoBase Output of I/O resource base address.\r
+ @param Mem32Base Output of 32-bit memory base address.\r
+ @param PMem32Base Output of 32-bit prefetchable memory base address.\r
+ @param Mem64Base Output of 64-bit memory base address.\r
+ @param PMem64Base Output of 64-bit prefetchable memory base address.\r
+\r
**/\r
-EFI_STATUS\r
+VOID\r
GetResourceBase (\r
- IN VOID *pConfig,\r
+ IN VOID *Config,\r
OUT UINT64 *IoBase,\r
OUT UINT64 *Mem32Base,\r
OUT UINT64 *PMem32Base,\r
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
UINT64 ResStatus;\r
\r
+ ASSERT (Config != NULL);\r
+\r
*IoBase = 0xFFFFFFFFFFFFFFFFULL;\r
*Mem32Base = 0xFFFFFFFFFFFFFFFFULL;\r
*PMem32Base = 0xFFFFFFFFFFFFFFFFULL;\r
*Mem64Base = 0xFFFFFFFFFFFFFFFFULL;\r
*PMem64Base = 0xFFFFFFFFFFFFFFFFULL;\r
\r
- Temp = (UINT8 *) pConfig;\r
+ Temp = (UINT8 *) Config;\r
\r
while (*Temp == ACPI_ADDRESS_SPACE_DESCRIPTOR) {\r
\r
// Check to see the granularity\r
//\r
if (Ptr->AddrSpaceGranularity == 32) {\r
- if (Ptr->SpecificFlag & 0x06) {\r
+ if ((Ptr->SpecificFlag & 0x06) != 0) {\r
*PMem32Base = Ptr->AddrRangeMin;\r
} else {\r
*Mem32Base = Ptr->AddrRangeMin;\r
}\r
\r
if (Ptr->AddrSpaceGranularity == 64) {\r
- if (Ptr->SpecificFlag & 0x06) {\r
+ if ((Ptr->SpecificFlag & 0x06) != 0) {\r
*PMem64Base = Ptr->AddrRangeMin;\r
} else {\r
*Mem64Base = Ptr->AddrRangeMin;\r
//\r
Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
/**\r
Enumerate pci bridge, allocate resource and determine attribute\r
- for devices on this bridge\r
- \r
- @param BridgeDev Pointer to instance of bridge device.\r
- \r
- @retval EFI_SUCCESS Success operation.\r
- @retval Others Fail to enumerate.\r
+ for devices on this bridge.\r
+\r
+ @param BridgeDev Pointer to instance of bridge device.\r
+\r
+ @retval EFI_SUCCESS Successfully enumerated PCI bridge.\r
+ @retval other Failed to enumerate.\r
+\r
**/\r
EFI_STATUS\r
PciBridgeEnumerator (\r
SubBusNumber = 0;\r
StartBusNumber = 0;\r
PciIo = &(BridgeDev->PciIo);\r
- Status = PciIoRead (PciIo, EfiPciIoWidthUint8, 0x19, 1, &StartBusNumber);\r
+ Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x19, 1, &StartBusNumber);\r
\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
/**\r
- Allocate all kinds of resource for bridge\r
- \r
- @param Bridge Pointer to bridge instance.\r
- \r
- @retval EFI_SUCCESS Success operation.\r
- @retval Others Fail to allocate resource for bridge.\r
+ Allocate all kinds of resource for PCI bridge.\r
+\r
+ @param Bridge Pointer to bridge instance.\r
+\r
+ @retval EFI_SUCCESS Successfully allocated resource for PCI bridge.\r
+ @retval other Failed to allocate resource for bridge.\r
+\r
**/\r
EFI_STATUS\r
PciBridgeResourceAllocator (\r
EFI_STATUS Status;\r
\r
IoBridge = CreateResourceNode (\r
- Bridge,\r
- 0,\r
- 0xFFF,\r
- 0,\r
- PciBarTypeIo16,\r
- PciResUsageTypical\r
- );\r
+ Bridge,\r
+ 0,\r
+ 0xFFF,\r
+ 0,\r
+ PciBarTypeIo16,\r
+ PciResUsageTypical\r
+ );\r
\r
Mem32Bridge = CreateResourceNode (\r
Bridge,\r
);\r
\r
PMem32Bridge = CreateResourceNode (\r
- Bridge,\r
- 0,\r
- 0xFFFFF,\r
- 0,\r
- PciBarTypePMem32,\r
- PciResUsageTypical\r
- );\r
+ Bridge,\r
+ 0,\r
+ 0xFFFFF,\r
+ 0,\r
+ PciBarTypePMem32,\r
+ PciResUsageTypical\r
+ );\r
\r
Mem64Bridge = CreateResourceNode (\r
Bridge,\r
);\r
\r
PMem64Bridge = CreateResourceNode (\r
- Bridge,\r
- 0,\r
- 0xFFFFF,\r
- 0,\r
- PciBarTypePMem64,\r
- PciResUsageTypical\r
- );\r
+ Bridge,\r
+ 0,\r
+ 0xFFFFF,\r
+ 0,\r
+ PciBarTypePMem64,\r
+ PciResUsageTypical\r
+ );\r
\r
//\r
// Create resourcemap by going through all the devices subject to this root bridge\r
//\r
- Status = CreateResourceMap (\r
- Bridge,\r
- IoBridge,\r
- Mem32Bridge,\r
- PMem32Bridge,\r
- Mem64Bridge,\r
- PMem64Bridge\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
+ CreateResourceMap (\r
+ Bridge,\r
+ IoBridge,\r
+ Mem32Bridge,\r
+ PMem32Bridge,\r
+ Mem64Bridge,\r
+ PMem64Bridge\r
+ );\r
\r
Status = GetResourceBaseFromBridge (\r
- Bridge,\r
- &IoBase,\r
- &Mem32Base,\r
- &PMem32Base,\r
- &Mem64Base,\r
- &PMem64Base\r
- );\r
+ Bridge,\r
+ &IoBase,\r
+ &Mem32Base,\r
+ &PMem32Base,\r
+ &Mem64Base,\r
+ &PMem64Base\r
+ );\r
\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
/**\r
- Get resource base address for a pci bridge device\r
- \r
- @param Bridge Given Pci driver instance.\r
- @param IoBase output for base address of I/O type resource.\r
- @param Mem32Base output for base address of 32-bit memory type resource.\r
- @param PMem32Base output for base address of 32-bit Pmemory type resource.\r
- @param Mem64Base output for base address of 64-bit memory type resource.\r
- @param PMem64Base output for base address of 64-bit Pmemory type resource.\r
- \r
- @retval EFI_SUCCESS Succes to get resource base address.\r
+ Get resource base address for a pci bridge device.\r
+\r
+ @param Bridge Given Pci driver instance.\r
+ @param IoBase Output for base address of I/O type resource.\r
+ @param Mem32Base Output for base address of 32-bit memory type resource.\r
+ @param PMem32Base Ooutput for base address of 32-bit Pmemory type resource.\r
+ @param Mem64Base Output for base address of 64-bit memory type resource.\r
+ @param PMem64Base Output for base address of 64-bit Pmemory type resource.\r
+\r
+ @retval EFI_SUCCESS Successfully got resource base address.\r
+ @retval EFI_OUT_OF_RESOURCES PCI bridge is not available.\r
+\r
**/\r
EFI_STATUS\r
GetResourceBaseFromBridge (\r
}\r
\r
/**\r
- These are the notifications from the PCI bus driver that it is about to enter a certain \r
+ These are the notifications from the PCI bus driver that it is about to enter a certain\r
phase of the PCI enumeration process.\r
\r
This member function can be used to notify the host bridge driver to perform specific actions,\r
including any chipset-specific initialization, so that the chipset is ready to enter the next phase.\r
Eight notification points are defined at this time. See belows:\r
- EfiPciHostBridgeBeginEnumeration - Resets the host bridge PCI apertures and internal data\r
+ EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data\r
structures. The PCI enumerator should issue this notification\r
before starting a fresh enumeration process. Enumeration cannot\r
be restarted after sending any other notification such as\r
EfiPciHostBridgeBeginBusAllocation.\r
- EfiPciHostBridgeBeginBusAllocation - The bus allocation phase is about to begin. No specific action is\r
+ EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is\r
required here. This notification can be used to perform any\r
chipset-specific programming.\r
- EfiPciHostBridgeEndBusAllocation - The bus allocation and bus programming phase is complete. No\r
+ EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No\r
specific action is required here. This notification can be used to\r
perform any chipset-specific programming.\r
- EfiPciHostBridgeBeginResourceAllocation - The resource allocation phase is about to begin. No specific\r
- action is required here. This notification can be used to perform\r
- any chipset-specific programming.\r
- EfiPciHostBridgeAllocateResources - Allocates resources per previously submitted requests for all the PCI\r
+ EfiPciHostBridgeBeginResourceAllocation\r
+ The resource allocation phase is about to begin. No specific\r
+ action is required here. This notification can be used to perform\r
+ any chipset-specific programming.\r
+ EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI\r
root bridges. These resource settings are returned on the next call to\r
GetProposedResources(). Before calling NotifyPhase() with a Phase of\r
- EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible for gathering I/O and memory requests for\r
+ EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible\r
+ for gathering I/O and memory requests for\r
all the PCI root bridges and submitting these requests using\r
SubmitResources(). This function pads the resource amount\r
to suit the root bridge hardware, takes care of dependencies between\r
the PCI root bridges, and calls the Global Coherency Domain (GCD)\r
with the allocation request. In the case of padding, the allocated range\r
could be bigger than what was requested.\r
- EfiPciHostBridgeSetResources - Programs the host bridge hardware to decode previously allocated\r
+ EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated\r
resources (proposed resources) for all the PCI root bridges. After the\r
hardware is programmed, reassigning resources will not be supported.\r
The bus settings are not affected.\r
- EfiPciHostBridgeFreeResources - Deallocates resources that were previously allocated for all the PCI\r
+ EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI\r
root bridges and resets the I/O and memory apertures to their initial\r
state. The bus settings are not affected. If the request to allocate\r
resources fails, the PCI enumerator can use this notification to\r
deallocate previous resources, adjust the requests, and retry\r
allocation.\r
- EfiPciHostBridgeEndResourceAllocation- The resource allocation phase is completed. No specific action is\r
+ EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is\r
required here. This notification can be used to perform any chipsetspecific\r
programming.\r
- \r
+\r
@param[in] PciResAlloc The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
@param[in] Phase The phase during enumeration\r
- \r
+\r
@retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error\r
is valid for a Phase of EfiPciHostBridgeAllocateResources if\r
SubmitResources() has not been called for one or more\r
HostBridgeHandle = PciRootBridgeIo->ParentHandle;\r
\r
//\r
- // Call PlatformPci::PhaseNotify() if the protocol is present.\r
+ // Call PlatformPci::PlatformNotify() if the protocol is present.\r
//\r
- gPciPlatformProtocol->PhaseNotify (\r
+ gPciPlatformProtocol->PlatformNotify (\r
gPciPlatformProtocol,\r
HostBridgeHandle,\r
Phase,\r
\r
if (gPciPlatformProtocol != NULL) {\r
//\r
- // Call PlatformPci::PhaseNotify() if the protocol is present.\r
+ // Call PlatformPci::PlatformNotify() if the protocol is present.\r
//\r
- gPciPlatformProtocol->PhaseNotify (\r
+ gPciPlatformProtocol->PlatformNotify (\r
gPciPlatformProtocol,\r
HostBridgeHandle,\r
Phase,\r
}\r
\r
/**\r
- Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various\r
- stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual\r
- PCI controllers before enumeration.\r
-\r
- This function is called during the PCI enumeration process. No specific action is expected from this\r
- member function. It allows the host bridge driver to preinitialize individual PCI controllers before\r
- enumeration.\r
-\r
- @param This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
- @param RootBridgeHandle The associated PCI root bridge handle. Type EFI_HANDLE is defined in\r
- InstallProtocolInterface() in the UEFI 2.0 Specification.\r
- @param PciAddress The address of the PCI device on the PCI bus. This address can be passed to the\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to access the PCI\r
- configuration space of the device. See Table 12-1 in the UEFI 2.0 Specification for\r
- the definition of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.\r
- @param Phase The phase of the PCI device enumeration. \r
- \r
- @retval EFI_SUCCESS The requested parameters were returned.\r
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
- @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in\r
- EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should\r
- not enumerate this device, including its child devices if it is a PCI-to-PCI\r
- bridge.\r
+ Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various\r
+ stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual\r
+ PCI controllers before enumeration.\r
+\r
+ This function is called during the PCI enumeration process. No specific action is expected from this\r
+ member function. It allows the host bridge driver to preinitialize individual PCI controllers before\r
+ enumeration.\r
+\r
+ @param Bridge Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
+ @param Bus The bus number of the pci device.\r
+ @param Device The device number of the pci device.\r
+ @param Func The function number of the pci device.\r
+ @param Phase The phase of the PCI device enumeration.\r
+\r
+ @retval EFI_SUCCESS The requested parameters were returned.\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
+ @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in\r
+ EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should\r
+ not enumerate this device, including its child devices if it is a PCI-to-PCI\r
+ bridge.\r
\r
**/\r
EFI_STATUS\r
}\r
\r
/**\r
- Hot plug request notify.\r
- \r
- @param This - A pointer to the hot plug request protocol.\r
- @param Operation - The operation.\r
- @param Controller - A pointer to the controller.\r
- @param RemainningDevicePath - A pointer to the device path.\r
- @param NumberOfChildren - A the number of child handle in the ChildHandleBuffer.\r
- @param ChildHandleBuffer - A pointer to the array contain the child handle.\r
- \r
- @retval EFI_NOT_FOUND Can not find bridge according to controller handle.\r
- @retval EFI_SUCCESS Success operating.\r
+ This function allows the PCI bus driver to be notified to act as requested when a hot-plug event has\r
+ happened on the hot-plug controller. Currently, the operations include add operation and remove operation..\r
+\r
+ @param This A pointer to the hot plug request protocol.\r
+ @param Operation The operation the PCI bus driver is requested to make.\r
+ @param Controller The handle of the hot-plug controller.\r
+ @param RemainingDevicePath The remaining device path for the PCI-like hot-plug device.\r
+ @param NumberOfChildren The number of child handles.\r
+ For a add operation, it is an output parameter.\r
+ For a remove operation, it's an input parameter.\r
+ @param ChildHandleBuffer The buffer which contains the child handles.\r
+\r
+ @retval EFI_INVALID_PARAMETER Operation is not a legal value.\r
+ Controller is NULL or not a valid handle.\r
+ NumberOfChildren is NULL.\r
+ ChildHandleBuffer is NULL while Operation is add.\r
+ @retval EFI_OUT_OF_RESOURCES There are no enough resources to start the devices.\r
+ @retval EFI_NOT_FOUND Can not find bridge according to controller handle.\r
+ @retval EFI_SUCCESS The handles for the specified device have been created or destroyed\r
+ as requested, and for an add operation, the new handles are\r
+ returned in ChildHandleBuffer.\r
**/\r
EFI_STATUS\r
EFIAPI\r
ChildHandleBuffer\r
);\r
\r
- return EFI_SUCCESS;\r
+ return Status;\r
}\r
\r
if (Operation == EfiPciHotplugRequestRemove) {\r
//\r
// Remove all devices on the bridge\r
//\r
- Status = RemoveAllPciDeviceOnBridge (RootBridgeHandle, Bridge);\r
- return Status;\r
+ RemoveAllPciDeviceOnBridge (RootBridgeHandle, Bridge);\r
+ return EFI_SUCCESS;\r
\r
}\r
\r
\r
/**\r
Search hostbridge according to given handle\r
- \r
- @return whether found\r
+\r
+ @param RootBridgeHandle Host bridge handle.\r
+\r
+ @retval TRUE Found host bridge handle.\r
+ @retval FALSE Not found hot bridge handle.\r
+\r
**/\r
BOOLEAN\r
SearchHostBridgeHandle (\r
}\r
\r
/**\r
- Add host bridge handle to global variable for enumating.\r
- \r
- @param HostBridgeHandle host bridge handle.\r
+ Add host bridge handle to global variable for enumerating.\r
+\r
+ @param HostBridgeHandle Host bridge handle.\r
+\r
+ @retval EFI_SUCCESS Successfully added host bridge.\r
+ @retval EFI_ABORTED Host bridge is NULL, or given host bridge\r
+ has been in host bridge list.\r
+\r
**/\r
EFI_STATUS\r
AddHostBridgeEnumerator (\r
projects / mirror_edk2.git / blobdiff