[Description]:

[mirror_edk2.git] / IntelFrameworkModulePkg / Bus / Pci / PciBusDxe / PciLib.c

diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.c b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.c
index d8cec4aaae9bfa6831f86327429bf49a628b28b2..d35fe0d042d752fb91f662e51f688d22f6d45fdd 100644 (file)
--- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.c
+++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.c
@@ -4,14 +4,14 @@
   It abstracts some functions that can be different\r
   between light PCI bus driver and full PCI bus driver\r
 \r
-Copyright (c) 2006, Intel Corporation                                                         \r
-All rights reserved. This program and the accompanying materials                          \r
-are licensed and made available under the terms and conditions of the BSD License         \r
-which accompanies this distribution.  The full text of the license may be found at        \r
-http://opensource.org/licenses/bsd-license.php                                            \r
-                                                                                          \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+Copyright (c) 2006 - 2008, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
 \r
 **/\r
 \r
@@ -1297,7 +1297,7 @@ Returns:
         //\r
         // Add feature to support customized secondary bus number\r
         //\r
-               if (*SubBusNumber == 0) {        \r
+               if (*SubBusNumber == 0) {\r
           *SubBusNumber   = *PaddedBusRange;\r
           *PaddedBusRange = 0;\r
         }\r
@@ -1481,7 +1481,7 @@ Returns:
       }\r
 \r
       DEBUG((EFI_D_ERROR, "Found DEV(%02d,%02d,%02d)\n", StartBusNumber, Device, Func ));\r
-      \r
+\r
       //\r
       // Get the PCI device information\r
       //\r
@@ -1594,7 +1594,7 @@ Returns:
         //\r
         // Add feature to support customized secondary bus number\r
         //\r
-               if (*SubBusNumber == 0) {        \r
+               if (*SubBusNumber == 0) {\r
           *SubBusNumber   = *PaddedBusRange;\r
           *PaddedBusRange = 0;\r
         }\r
@@ -1860,9 +1860,15 @@ Returns:
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL   *PciRootBridgeIo;\r
   UINT16                            MinBus;\r
   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
+  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *pConfiguration;\r
+  UINT8                             StartBusNumber;\r
+  LIST_ENTRY                        RootBridgeList;\r
+  LIST_ENTRY                        *Link;\r
 \r
   InitializeHotPlugSupport ();\r
 \r
+  InitializeListHead (&RootBridgeList);\r
+\r
   //\r
   // Notify the bus allocation phase is about to start\r
   //\r
@@ -1891,7 +1897,11 @@ Returns:
               RootBridgeDev\r
               );\r
 \r
-    DestroyRootBridge (RootBridgeDev);\r
+    if (gPciHotPlugInit != NULL) {\r
+      InsertTailList (&RootBridgeList, &(RootBridgeDev->Link));\r
+    } else {\r
+      DestroyRootBridge (RootBridgeDev);\r
+    }\r
     if (EFI_ERROR (Status)) {\r
       return Status;\r
     }\r
@@ -1906,8 +1916,43 @@ Returns:
 \r
     if (gPciHotPlugInit != NULL) {\r
       //\r
-      // Wait for all HPC initialized\r
+      // Reset all assigned PCI bus number in all PPB\r
+      //\r
+      RootBridgeHandle = NULL;\r
+      Link = GetFirstNode (&RootBridgeList);\r
+      while ((PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) &&\r
+        (!IsNull (&RootBridgeList, Link))) {\r
+        RootBridgeDev = PCI_IO_DEVICE_FROM_LINK (Link);\r
+        //\r
+        // Get the Bus information\r
+        //\r
+        Status = PciResAlloc->StartBusEnumeration (\r
+                                PciResAlloc,\r
+                                RootBridgeHandle,\r
+                                (VOID **) &pConfiguration\r
+                                );\r
+        if (EFI_ERROR (Status)) {\r
+          return Status;\r
+        }\r
+\r
+        //\r
+        // Get the bus number to start with\r
+        //\r
+        StartBusNumber  = (UINT8) (pConfiguration->AddrRangeMin);\r
+\r
+        ResetAllPpbBusNumber (\r
+          RootBridgeDev,\r
+          StartBusNumber\r
+        );\r
+\r
+        gBS->FreePool (pConfiguration);\r
+        Link = GetNextNode (&RootBridgeList, Link);\r
+        DestroyRootBridge (RootBridgeDev);\r
+      }\r
+\r
       //\r
+      // Wait for all HPC initialized\r
+     //\r
       Status = AllRootHPCInitialized (STALL_1_SECOND * 15);\r
 \r
       if (EFI_ERROR (Status)) {\r
@@ -1919,7 +1964,7 @@ Returns:
       //\r
       NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginBusAllocation);\r
 \r
-      DEBUG((EFI_D_ERROR, "PCI Bus Second Scanning\n"));  \r
+      DEBUG((EFI_D_ERROR, "PCI Bus Second Scanning\n"));\r
       RootBridgeHandle = NULL;\r
       while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
 \r