SecondBus = 0;\r
Register = 0;\r
\r
- ResetAllPpbBusReg (Bridge, StartBusNumber);\r
-\r
for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r
\r
(IS_PCI_BRIDGE (&Pci) ||\r
IS_CARDBUS_BRIDGE (&Pci))) {\r
\r
+ DEBUG((EFI_D_ERROR, "Found DEV(%02d,%02d,%02d)\n", StartBusNumber, Device, Func ));\r
+\r
//\r
// Get the bridge information\r
//\r
return Status;\r
}\r
\r
+ //\r
+ // Add feature to support customized secondary bus number\r
+ //\r
+ if (*SubBusNumber == 0) { \r
+ *SubBusNumber = *PaddedBusRange;\r
+ *PaddedBusRange = 0;\r
+ }\r
+\r
(*SubBusNumber)++;\r
\r
SecondBus = (*SubBusNumber);\r
EfiPciBeforeChildBusEnumeration\r
);\r
\r
+ DEBUG((EFI_D_ERROR, "Scan PPB(%02d,%02d,%02d)\n", PciDevice->BusNumber, PciDevice->DeviceNumber,PciDevice->FunctionNumber ));\r
Status = PciScanBus (\r
PciDevice,\r
(UINT8) (SecondBus),\r
Attributes = (EFI_HPC_PADDING_ATTRIBUTES) 0;\r
BusRange = 0;\r
\r
- ResetAllPpbBusReg (Bridge, StartBusNumber);\r
-\r
for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r
\r
continue;\r
}\r
\r
+ DEBUG((EFI_D_ERROR, "Found DEV(%02d,%02d,%02d)\n", StartBusNumber, Device, Func ));\r
+ \r
//\r
// Get the PCI device information\r
//\r
PciDevice->FunctionNumber,\r
EfiPciBeforeChildBusEnumeration\r
);\r
- continue;\r
}\r
}\r
}\r
}\r
}\r
\r
+ //\r
+ // Add feature to support customized secondary bus number\r
+ //\r
+ if (*SubBusNumber == 0) { \r
+ *SubBusNumber = *PaddedBusRange;\r
+ *PaddedBusRange = 0;\r
+ }\r
+\r
(*SubBusNumber)++;\r
SecondBus = *SubBusNumber;\r
\r
EfiPciBeforeChildBusEnumeration\r
);\r
\r
+ DEBUG((EFI_D_ERROR, "Scan PPB(%02d,%02d,%02d)\n", PciDevice->BusNumber, PciDevice->DeviceNumber,PciDevice->FunctionNumber ));\r
Status = PciScanBus (\r
PciDevice,\r
(UINT8) (SecondBus),\r
//\r
NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginBusAllocation);\r
\r
+ DEBUG((EFI_D_ERROR, "PCI Bus First Scanning\n"));\r
RootBridgeHandle = NULL;\r
while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
\r
//\r
NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginBusAllocation);\r
\r
+ DEBUG((EFI_D_ERROR, "PCI Bus Second Scanning\n")); \r
RootBridgeHandle = NULL;\r
while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
\r
\r
Stride = 1 << AccessWidth;\r
AccessAddress += Stride;\r
- if (AccessAddress >= (Address + (1 << Width))) {\r
+ if (AccessAddress >= (Address + LShiftU64 (1ULL, (UINTN)Width))) {\r
//\r
// if all datas have been read, exist\r
//\r
\r
Stride = 1 << AccessWidth;\r
AccessAddress += Stride;\r
- if (AccessAddress >= (Address + (1 << Width))) {\r
+ if (AccessAddress >= (Address + LShiftU64 (1ULL, (UINTN)Width))) {\r
//\r
// if all datas have been written, exist\r
//\r