Update CSM module to provide the general solution when the Timer Arch Protocol is...

[mirror_edk2.git] / IntelFrameworkModulePkg / Csm / LegacyBiosDxe / LegacyBiosInterface.h

diff --git a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h
index 15b3b7048cf99548dcc85a8a617f65b23cec20db..8ab26fe3262515a9b6fef292133a9fda92793e59 100644 (file)
--- a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h
+++ b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h
@@ -29,6 +29,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #include <Protocol/LoadedImage.h>\r
 #include <Protocol/PciIo.h>\r
 #include <Protocol/Cpu.h>\r
+#include <Protocol/Timer.h>\r
 #include <Protocol/IsaIo.h>\r
 #include <Protocol/LegacyRegion2.h>\r
 #include <Protocol/SimpleTextIn.h>\r
@@ -517,6 +518,18 @@ extern UINTN               mEndOpromShadowAddress;
 #define CMOS_31     0x31  ///< CMOS 0x18\r
 #define CMOS_32     0x32  ///< Century byte\r
 \r
+//\r
+// 8254 Timer registers\r
+//\r
+#define TIMER0_COUNT_PORT                         0x40\r
+#define TIMER1_COUNT_PORT                         0x41\r
+#define TIMER2_COUNT_PORT                         0x42\r
+#define TIMER_CONTROL_PORT                        0x43\r
+\r
+//\r
+// Timer 0, Read/Write LSB then MSB, Square wave output, binary count use.\r
+//\r
+#define TIMER0_CONTROL_WORD         0x36      \r
 \r
 #define LEGACY_BIOS_INSTANCE_SIGNATURE  SIGNATURE_32 ('L', 'B', 'I', 'T')\r
 typedef struct {\r
@@ -532,6 +545,12 @@ typedef struct {
   //\r
   EFI_CPU_ARCH_PROTOCOL             *Cpu;\r
 \r
+  //\r
+  // Timer Architectural Protocol \r
+  //\r
+  EFI_TIMER_ARCH_PROTOCOL           *Timer;\r
+  BOOLEAN                           TimerUses8254; \r
+  \r
   //\r
   // Protocol to Lock and Unlock 0xc0000 - 0xfffff\r
   //\r
@@ -543,7 +562,7 @@ typedef struct {
   // Interrupt control for thunk and PCI IRQ\r
   //\r
   EFI_LEGACY_8259_PROTOCOL          *Legacy8259;\r
-\r
+  \r
   //\r
   // PCI Interrupt PIRQ control\r
   //\r