/** @file\r
Call into 16-bit BIOS code, Use AsmThunk16 function of BaseLib.\r
\r
-Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
IN EFI_IA32_REGISTER_SET *Regs\r
)\r
{\r
- UINT32 *VectorBase;\r
+ UINT16 Segment;\r
+ UINT16 Offset;\r
\r
Regs->X.Flags.Reserved1 = 1;\r
Regs->X.Flags.Reserved2 = 0;\r
// The base address of legacy interrupt vector table is 0.\r
// We use this base address to get the legacy interrupt handler.\r
//\r
- VectorBase = 0;\r
- \r
+ ACCESS_PAGE0_CODE (\r
+ Segment = (UINT16)(((UINT32 *)0)[BiosInt] >> 16);\r
+ Offset = (UINT16)((UINT32 *)0)[BiosInt];\r
+ );\r
+\r
return InternalLegacyBiosFarCall (\r
This,\r
- (UINT16) ((VectorBase)[BiosInt] >> 16),\r
- (UINT16) (VectorBase)[BiosInt],\r
+ Segment,\r
+ Offset,\r
Regs,\r
&Regs->X.Flags,\r
sizeof (Regs->X.Flags)\r
}\r
\r
/**\r
- Provide NULL interrupt handler which is used to check \r
+ Provide NULL interrupt handler which is used to check\r
if there is more than one HW interrupt registers with the CPU AP.\r
\r
@param InterruptType - The type of interrupt that occured\r
// Disable DXE Timer while executing in real mode\r
//\r
Private->Timer->SetTimerPeriod (Private->Timer, 0);\r
- \r
+\r
//\r
// Save and disable interrupt of debug timer\r
//\r
\r
//\r
// Check to see if there is more than one HW interrupt registers with the CPU AP.\r
- // If there is, then ASSERT() since that is not compatible with the CSM because \r
- // interupts other than the Timer interrupt that was disabled above can not be \r
+ // If there is, then ASSERT() since that is not compatible with the CSM because\r
+ // interupts other than the Timer interrupt that was disabled above can not be\r
// handled properly from real mode.\r
//\r
DEBUG_CODE (\r
UINTN Vector;\r
UINTN Count;\r
- \r
+\r
for (Vector = 0x20, Count = 0; Vector < 0x100; Vector++) {\r
Status = Private->Cpu->RegisterInterruptHandler (Private->Cpu, Vector, LegacyBiosNullInterruptHandler);\r
if (Status == EFI_ALREADY_STARTED) {\r
);\r
\r
//\r
- // If the Timer AP has enabled the 8254 timer IRQ and the current 8254 timer \r
- // period is less than the CSM required rate of 54.9254, then force the 8254 \r
+ // If the Timer AP has enabled the 8254 timer IRQ and the current 8254 timer\r
+ // period is less than the CSM required rate of 54.9254, then force the 8254\r
// PIT counter to 0, which is the CSM required rate of 54.9254 ms\r
//\r
if (Private->TimerUses8254 && TimerPeriod < 549254) {\r
SetPitCount (0);\r
}\r
- \r
+\r
if (Stack != NULL && StackSize != 0) {\r
//\r
// Copy Stack to low memory stack\r
\r
AsmThunk16 (&mThunkContext);\r
\r
- //\r
- // OPROM may allocate EBDA range by itself and change EBDA base and EBDA size.\r
- // Get the current EBDA base address, and compared with pre-allocate minimum\r
- // EBDA base address, if the current EBDA base address is smaller, it indicates\r
- // PcdEbdaReservedMemorySize should be adjusted to larger for more OPROMs.\r
- //\r
- DEBUG_CODE (\r
- {\r
- UINTN EbdaBaseAddress;\r
- UINTN ReservedEbdaBaseAddress;\r
-\r
- EbdaBaseAddress = (*(UINT16 *) (UINTN) 0x40E) << 4;\r
- ReservedEbdaBaseAddress = CONVENTIONAL_MEMORY_TOP - PcdGet32 (PcdEbdaReservedMemorySize);\r
- ASSERT (ReservedEbdaBaseAddress <= EbdaBaseAddress);\r
- }\r
- );\r
-\r
if (Stack != NULL && StackSize != 0) {\r
//\r
// Copy low memory stack to Stack\r
// End critical section\r
//\r
gBS->RestoreTPL (OriginalTpl);\r
- \r
+\r
+ //\r
+ // OPROM may allocate EBDA range by itself and change EBDA base and EBDA size.\r
+ // Get the current EBDA base address, and compared with pre-allocate minimum\r
+ // EBDA base address, if the current EBDA base address is smaller, it indicates\r
+ // PcdEbdaReservedMemorySize should be adjusted to larger for more OPROMs.\r
+ //\r
+ DEBUG_CODE (\r
+ {\r
+ UINTN EbdaBaseAddress;\r
+ UINTN ReservedEbdaBaseAddress;\r
+\r
+ ACCESS_PAGE0_CODE (\r
+ EbdaBaseAddress = (*(UINT16 *) (UINTN) 0x40E) << 4;\r
+ ReservedEbdaBaseAddress = CONVENTIONAL_MEMORY_TOP\r
+ - PcdGet32 (PcdEbdaReservedMemorySize);\r
+ ASSERT (ReservedEbdaBaseAddress <= EbdaBaseAddress);\r
+ );\r
+ }\r
+ );\r
+\r
//\r
// Restore interrupt of debug timer\r
//\r
TimerVector = 0;\r
Status = Private->Legacy8259->GetVector (Private->Legacy8259, Efi8259Irq0, &TimerVector);\r
ASSERT_EFI_ERROR (Status);\r
- \r
+\r
//\r
// Check to see if the Timer AP has hooked the IRQ0 from the 8254 PIT\r
- // \r
+ //\r
Status = Private->Cpu->RegisterInterruptHandler (\r
- Private->Cpu, \r
- TimerVector, \r
+ Private->Cpu,\r
+ TimerVector,\r
LegacyBiosNullInterruptHandler\r
);\r
if (Status == EFI_SUCCESS) {\r
//\r
- // If the Timer AP has not enabled the 8254 timer IRQ, then force the 8254 PIT \r
+ // If the Timer AP has not enabled the 8254 timer IRQ, then force the 8254 PIT\r
// counter to 0, which is the CSM required rate of 54.9254 ms\r
//\r
Private->Cpu->RegisterInterruptHandler (\r
- Private->Cpu, \r
- TimerVector, \r
+ Private->Cpu,\r
+ TimerVector,\r
NULL\r
);\r
SetPitCount (0);\r
- \r
+\r
//\r
// Save status that the Timer AP is not using the 8254 PIT\r
//\r
//\r
ASSERT (FALSE);\r
}\r
- \r
+\r
return EFI_SUCCESS;\r
}\r
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