+\r
+[PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]\r
+ ## The 4 PCDs below are used to specify the video resolution and text mode of text setup.\r
+ # To make text setup work in this resolution, PcdVideoHorizontalResolution, PcdVideoVerticalResolution,\r
+ # PcdConOutColumn and PcdConOutRow in MdeModulePkg.dec should be created as PcdsDynamic or PcdsDynamicEx\r
+ # in platform DSC file. Then BDS setup will update these PCDs defined in MdeModulePkg.dec and reconnect\r
+ # console drivers (GraphicsConsole, Terminal, Consplitter) to make the video resolution and text mode work\r
+ # for text setup.\r
+\r
+ ## The PCD is used to specify the video horizontal resolution of text setup. \r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|800|UINT32|0x50000001\r
+ \r
+ ## The PCD is used to specify the video vertical resolution of text setup.\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|600|UINT32|0x50000002\r
+\r
+ ## The PCD is used to specify the console output column of text setup.\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdSetupConOutColumn|80|UINT32|0x50000003\r
+ \r
+ ## The PCD is used to specify the console output column of text setup.\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdSetupConOutRow|25|UINT32|0x50000004\r
+\r
+[PcdsFixedAtBuild, PcdsDynamic, PcdsDynamicEx, PcdsPatchableInModule]\r
+ ## I/O Base address of floppy device controller.\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdFdcBaseAddress|0x3f0|UINT16|0x30000000\r
+\r
+ ## If TRUE, BiosVideo will switch to 80x25 Text VGA Mode when exiting boot service.\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBiosVideoSetTextVgaModeEnable|FALSE|BOOLEAN|0x30000001\r
+\r
+ ## If TRUE, BiosVideo will check for VESA BIOS Extension service support.\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBiosVideoCheckVbeEnable|TRUE|BOOLEAN|0x30000002\r
+\r
+ ## If TRUE, BiosVideo will check for VGA service support.\r
+ # NOTE: If both PcdBiosVideoCheckVbeEnable and PcdBiosVideoCheckVgaEnable are set to FALSE,\r
+ # that means Graphics Output protocol will not be installed, the VGA miniport protocol will be installed instead.\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBiosVideoCheckVgaEnable|TRUE|BOOLEAN|0x30000003\r
+\r
+ ## If TRUE, memory space for legacy region will be set as cacheable.\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLegacyBiosCacheLegacyRegion|TRUE|BOOLEAN|0x00000004\r
+\r
+ ## The PCD is used to specify memory size with bytes to reserve EBDA for OPROM.\r
+ ## The value should be a multiple of 4KB.\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdEbdaReservedMemorySize|0x8000|UINT32|0x30000005\r
+\r
+ ## The PCD is used to specify memory base address for OPROM to find free memory.\r
+ # Some OPROMs do not use EBDA or PMM to allocate memory for its usage, \r
+ # instead they find the memory filled with zero from 0x20000.\r
+ # The value should be a multiple of 4KB.\r
+ # The range should be below the EBDA reserved range from \r
+ # (CONVENTIONAL_MEMORY_TOP - PcdEbdaReservedMemorySize) to CONVENTIONAL_MEMORY_TOP.\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdOpromReservedMemoryBase|0x60000|UINT32|0x3000000c\r
+ \r
+ ## The PCD is used to specify memory size with bytes for OPROM to find free memory.\r
+ ## The value should be a multiple of 4KB. And the range should be below the EBDA reserved range from \r
+ # (CONVENTIONAL_MEMORY_TOP - PcdEbdaReservedMemorySize) to CONVENTIONAL_MEMORY_TOP.\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdOpromReservedMemorySize|0x28000|UINT32|0x3000000d\r
+\r
+ ## The PCD is used to specify memory size with page number for a pre-allocated reserved memory to be used\r
+ # by PEI in S3 phase. The default size 32K. When changing the value of this PCD, the platform\r
+ # developer should make sure the memory size is large enough to meet PEI requiremnt in S3 phase.\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0x8000|UINT32|0x30000006\r
+\r
+ ## The PCD is used to specify memory size for boot script executor stack usage in S3 phase.\r
+ # The default size 32K. When changing the value of this PCD, the platform developer should\r
+ # make sure the memory size is large enough to meet boot script executor requiremnt in S3 phase.\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdS3BootScriptStackSize|0x8000|UINT32|0x30000007\r
+\r
+ ## The PCD is used to specify the end of address below 1MB for the OPROM.\r
+ # The last shadowed OpROM should not exceed this address.\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdEndOpromShadowAddress|0xdffff|UINT32|0x30000008\r
+ \r
+ ## The PCD is used to specify the low PMM (Post Memory Manager) size with bytes below 1MB.\r
+ # The value should be a multiple of 4KB.\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLowPmmMemorySize|0x10000|UINT32|0x30000009\r
+ \r
+ ## The PCD is used to specify the high PMM (Post Memory Manager) size with bytes above 1MB.\r
+ # The value should be a multiple of 4KB.\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdHighPmmMemorySize|0x400000|UINT32|0x3000000a\r
+\r
+ ## This PCD specifies whether to use the optimized timing for best PS2 detection performance.\r
+ # Note this PCD could be set to TRUE for best boot performance and set to FALSE for best device compatibility.\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdFastPS2Detection|FALSE|BOOLEAN|0x3000000b\r