--- /dev/null
+/** @file\r
+ The incompatible PCI device list\r
+\r
+Copyright (c) 2007 Intel Corporation. All rights reserved. <BR>\r
+This software and associated documentation (if any) is furnished\r
+under a license and may only be used or copied in accordance\r
+with the terms of the license. Except as permitted by such\r
+license, no part of this software or documentation may be\r
+reproduced, stored in a retrieval system, or transmitted in any\r
+form or by any means without the express written consent of\r
+Intel Corporation.\r
+\r
+**/\r
+\r
+#ifndef _EFI_INCOMPATIBLE_PCI_DEVICE_LIST_H\r
+#define _EFI_INCOMPATIBLE_PCI_DEVICE_LIST_H\r
+\r
+//\r
+// Include common header file for this module.\r
+//\r
+#include "CommonHeader.h"\r
+\r
+#include <IndustryStandard/pci22.h>\r
+#include <IndustryStandard/Acpi.h>\r
+\r
+\r
+#define PCI_DEVICE_ID(VendorId, DeviceId, Revision, SubVendorId, SubDeviceId) \\r
+ VendorId, DeviceId, Revision, SubVendorId, SubDeviceId\r
+\r
+#define PCI_BAR_TYPE_IO ACPI_ADDRESS_SPACE_TYPE_IO\r
+#define PCI_BAR_TYPE_MEM ACPI_ADDRESS_SPACE_TYPE_MEM\r
+\r
+#define DEVICE_INF_TAG 0xFFF2\r
+#define DEVICE_RES_TAG 0xFFF1\r
+#define LIST_END_TAG 0x0000\r
+\r
+//\r
+// descriptor for access width of incompatible PCI device\r
+//\r
+typedef struct {\r
+ UINT64 AccessType;\r
+ UINT64 AccessWidth;\r
+ EFI_PCI_REGISTER_ACCESS_DATA PciRegisterAccessData;\r
+} EFI_PCI_REGISTER_ACCESS_DESCRIPTOR;\r
+\r
+//\r
+// descriptor for register value of incompatible PCI device\r
+//\r
+typedef struct {\r
+ UINT64 AccessType;\r
+ UINT64 Offset;\r
+ EFI_PCI_REGISTER_VALUE_DATA PciRegisterValueData;\r
+} EFI_PCI_REGISTER_VALUE_DESCRIPTOR;\r
+\r
+\r
+//\r
+// the incompatible PCI devices list for ACPI resource\r
+//\r
+GLOBAL_REMOVE_IF_UNREFERENCED UINT64 IncompatiblePciDeviceListForResource[] = {\r
+ //\r
+ // DEVICE_INF_TAG,\r
+ // PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),\r
+ // DEVICE_RES_TAG,\r
+ // ResType, GFlag , SFlag, Granularity, RangeMin,\r
+ // RangeMax, Offset, AddrLen\r
+ //\r
+ //\r
+ // Device Adaptec 9004\r
+ //\r
+ DEVICE_INF_TAG,\r
+ PCI_DEVICE_ID(0x9004, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
+ DEVICE_RES_TAG,\r
+ PCI_BAR_TYPE_IO,\r
+ PCI_ACPI_UNUSED,\r
+ PCI_ACPI_UNUSED,\r
+ PCI_ACPI_UNUSED,\r
+ PCI_ACPI_UNUSED,\r
+ PCI_BAR_EVEN_ALIGN,\r
+ PCI_BAR_ALL,\r
+ PCI_BAR_NOCHANGE,\r
+ //\r
+ // Device Adaptec 9005\r
+ //\r
+ DEVICE_INF_TAG,\r
+ PCI_DEVICE_ID(0x9005, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
+ DEVICE_RES_TAG,\r
+ PCI_BAR_TYPE_IO,\r
+ PCI_ACPI_UNUSED,\r
+ PCI_ACPI_UNUSED,\r
+ PCI_ACPI_UNUSED,\r
+ PCI_ACPI_UNUSED,\r
+ PCI_BAR_EVEN_ALIGN,\r
+ PCI_BAR_ALL,\r
+ PCI_BAR_NOCHANGE,\r
+ //\r
+ // Device QLogic 1007\r
+ //\r
+ DEVICE_INF_TAG,\r
+ PCI_DEVICE_ID(0x1077, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
+ DEVICE_RES_TAG,\r
+ PCI_BAR_TYPE_IO,\r
+ PCI_ACPI_UNUSED,\r
+ PCI_ACPI_UNUSED,\r
+ PCI_ACPI_UNUSED,\r
+ PCI_ACPI_UNUSED,\r
+ PCI_BAR_EVEN_ALIGN,\r
+ PCI_BAR_ALL,\r
+ PCI_BAR_NOCHANGE,\r
+ //\r
+ // Device Agilent 103C\r
+ //\r
+ DEVICE_INF_TAG,\r
+ PCI_DEVICE_ID(0x103C, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
+ DEVICE_RES_TAG,\r
+ PCI_BAR_TYPE_IO,\r
+ PCI_ACPI_UNUSED,\r
+ PCI_ACPI_UNUSED,\r
+ PCI_ACPI_UNUSED,\r
+ PCI_ACPI_UNUSED,\r
+ PCI_BAR_EVEN_ALIGN,\r
+ PCI_BAR_ALL,\r
+ PCI_BAR_NOCHANGE,\r
+ //\r
+ // Device Agilent 15BC\r
+ //\r
+ DEVICE_INF_TAG,\r
+ PCI_DEVICE_ID(0x15BC, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
+ DEVICE_RES_TAG,\r
+ PCI_BAR_TYPE_IO,\r
+ PCI_ACPI_UNUSED,\r
+ PCI_ACPI_UNUSED,\r
+ PCI_ACPI_UNUSED,\r
+ PCI_ACPI_UNUSED,\r
+ PCI_BAR_EVEN_ALIGN,\r
+ PCI_BAR_ALL,\r
+ PCI_BAR_NOCHANGE,\r
+ //\r
+ // The end of the list\r
+ //\r
+ LIST_END_TAG\r
+};\r
+\r
+//\r
+// the incompatible PCI devices list for the values of configuration registers\r
+//\r
+GLOBAL_REMOVE_IF_UNREFERENCED UINT64 IncompatiblePciDeviceListForRegister[] = {\r
+ //\r
+ // DEVICE_INF_TAG,\r
+ // PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),\r
+ // PCI_RES_TAG,\r
+ // PCI_ACCESS_TYPE, PCI_CONFIG_ADDRESS,\r
+ // AND_VALUE, OR_VALUE\r
+\r
+ //\r
+ // Device Lava 0x1407, DeviceId 0x0110\r
+ //\r
+ DEVICE_INF_TAG,\r
+ PCI_DEVICE_ID(0x1407, 0x0110, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
+ DEVICE_RES_TAG,\r
+ PCI_REGISTER_READ,\r
+ PCI_CAPBILITY_POINTER_OFFSET,\r
+ 0xffffff00,\r
+ VALUE_NOCARE,\r
+\r
+ //\r
+ // Device Lava 0x1407, DeviceId 0x0111\r
+ //\r
+ DEVICE_INF_TAG,\r
+ PCI_DEVICE_ID(0x1407, 0x0111, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
+ DEVICE_RES_TAG,\r
+ PCI_REGISTER_READ,\r
+ PCI_CAPBILITY_POINTER_OFFSET,\r
+ 0xffffff00,\r
+ VALUE_NOCARE,\r
+\r
+ //\r
+ // The end of the list\r
+ //\r
+ LIST_END_TAG\r
+};\r
+\r
+//\r
+// the incompatible PCI devices list for the access width of configuration registers\r
+//\r
+GLOBAL_REMOVE_IF_UNREFERENCED UINT64 DeviceListForAccessWidth[] = {\r
+ //\r
+ // DEVICE_INF_TAG,\r
+ // PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),\r
+ // DEVICE_RES_TAG,\r
+ // PCI_ACCESS_TYPE, PCI_ACCESS_WIDTH,\r
+ // START_ADDRESS, END_ADDRESS,\r
+ // ACTUAL_PCI_ACCESS_WIDTH,\r
+ //\r
+\r
+ //\r
+ // Sample Device\r
+ //\r
+ //DEVICE_INF_TAG,\r
+ //PCI_DEVICE_ID(0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
+ //DEVICE_RES_TAG,\r
+ //PCI_REGISTER_READ,\r
+ //EfiPciWidthUint8,\r
+ //0,\r
+ //0xFF,\r
+ //EfiPciWidthUint32,\r
+ //\r
+\r
+ //\r
+ // The end of the list\r
+ //\r
+ LIST_END_TAG\r
+};\r
+\r
+#endif\r
projects / mirror_edk2.git / blobdiff