+++ /dev/null
-/** @file\r
- Uses the services of the I/O Library to produce the CPU I/O Protocol\r
-\r
-Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>\r
-Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
-\r
-SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
-**/\r
-\r
-#include "CpuIo.h"\r
-\r
-//\r
-// Handle for the CPU I/O Protocol\r
-//\r
-EFI_HANDLE mHandle = NULL;\r
-\r
-//\r
-// CPU I/O Protocol inatance\r
-//\r
-EFI_CPU_IO_PROTOCOL mCpuIo = {\r
- {\r
- CpuMemoryServiceRead,\r
- CpuMemoryServiceWrite\r
- },\r
- {\r
- CpuIoServiceRead,\r
- CpuIoServiceWrite\r
- }\r
-};\r
-\r
-//\r
-// Lookup table for increment values based on transfer widths\r
-//\r
-UINT8 mInStride[] = {\r
- 1, // EfiCpuIoWidthUint8\r
- 2, // EfiCpuIoWidthUint16\r
- 4, // EfiCpuIoWidthUint32\r
- 8, // EfiCpuIoWidthUint64\r
- 0, // EfiCpuIoWidthFifoUint8\r
- 0, // EfiCpuIoWidthFifoUint16\r
- 0, // EfiCpuIoWidthFifoUint32\r
- 0, // EfiCpuIoWidthFifoUint64\r
- 1, // EfiCpuIoWidthFillUint8\r
- 2, // EfiCpuIoWidthFillUint16\r
- 4, // EfiCpuIoWidthFillUint32\r
- 8 // EfiCpuIoWidthFillUint64\r
-};\r
-\r
-//\r
-// Lookup table for increment values based on transfer widths\r
-//\r
-UINT8 mOutStride[] = {\r
- 1, // EfiCpuIoWidthUint8\r
- 2, // EfiCpuIoWidthUint16\r
- 4, // EfiCpuIoWidthUint32\r
- 8, // EfiCpuIoWidthUint64\r
- 1, // EfiCpuIoWidthFifoUint8\r
- 2, // EfiCpuIoWidthFifoUint16\r
- 4, // EfiCpuIoWidthFifoUint32\r
- 8, // EfiCpuIoWidthFifoUint64\r
- 0, // EfiCpuIoWidthFillUint8\r
- 0, // EfiCpuIoWidthFillUint16\r
- 0, // EfiCpuIoWidthFillUint32\r
- 0 // EfiCpuIoWidthFillUint64\r
-};\r
-\r
-/**\r
- Check parameters to a CPU I/O Protocol service request.\r
-\r
- The I/O operations are carried out exactly as requested. The caller is responsible\r
- for satisfying any alignment and I/O width restrictions that a PI System on a\r
- platform might require. For example on some platforms, width requests of\r
- EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
- be handled by the driver.\r
-\r
- @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port operation.\r
- @param[in] Width Signifies the width of the I/O or Memory operation.\r
- @param[in] Address The base address of the I/O operation.\r
- @param[in] Count The number of I/O operations to perform. The number of\r
- bytes moved is Width size * Count, starting at Address.\r
- @param[in] Buffer For read operations, the destination buffer to store the results.\r
- For write operations, the source buffer from which to write data.\r
-\r
- @retval EFI_SUCCESS The parameters for this request pass the checks.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
- and Count is not valid for this PI system.\r
-\r
-**/\r
-EFI_STATUS\r
-CpuIoCheckParameter (\r
- IN BOOLEAN MmioOperation,\r
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- )\r
-{\r
- UINT64 MaxCount;\r
- UINT64 Limit;\r
-\r
- //\r
- // Check to see if Buffer is NULL\r
- //\r
- if (Buffer == NULL) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- //\r
- // Check to see if Width is in the valid range\r
- //\r
- if ((UINT32)Width >= EfiCpuIoWidthMaximum) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- //\r
- // For FIFO type, the target address won't increase during the access,\r
- // so treat Count as 1\r
- //\r
- if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {\r
- Count = 1;\r
- }\r
-\r
- //\r
- // Check to see if Width is in the valid range for I/O Port operations\r
- //\r
- Width = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
- if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- //\r
- // Check to see if Address is aligned\r
- //\r
- if ((Address & ((UINT64)mInStride[Width] - 1)) != 0) {\r
- return EFI_UNSUPPORTED;\r
- }\r
-\r
- //\r
- // Check to see if any address associated with this transfer exceeds the maximum\r
- // allowed address. The maximum address implied by the parameters passed in is\r
- // Address + Size * Count. If the following condition is met, then the transfer\r
- // is not supported.\r
- //\r
- // Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1\r
- //\r
- // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count\r
- // can also be the maximum integer value supported by the CPU, this range\r
- // check must be adjusted to avoid all overflow conditions.\r
- //\r
- // The following form of the range check is equivalent but assumes that\r
- // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1).\r
- //\r
- Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS);\r
- if (Count == 0) {\r
- if (Address > Limit) {\r
- return EFI_UNSUPPORTED;\r
- }\r
- } else {\r
- MaxCount = RShiftU64 (Limit, Width);\r
- if (MaxCount < (Count - 1)) {\r
- return EFI_UNSUPPORTED;\r
- }\r
- if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {\r
- return EFI_UNSUPPORTED;\r
- }\r
- }\r
-\r
- //\r
- // Check to see if Buffer is aligned\r
- // (IA-32 allows UINT64 and INT64 data types to be 32-bit aligned.)\r
- //\r
- if (((UINTN)Buffer & ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != 0) {\r
- return EFI_UNSUPPORTED;\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Reads memory-mapped registers.\r
-\r
- The I/O operations are carried out exactly as requested. The caller is responsible\r
- for satisfying any alignment and I/O width restrictions that a PI System on a\r
- platform might require. For example on some platforms, width requests of\r
- EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
- be handled by the driver.\r
-\r
- If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
- or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
- each of the Count operations that is performed.\r
-\r
- If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
- EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
- incremented for each of the Count operations that is performed. The read or\r
- write operation is performed Count times on the same Address.\r
-\r
- If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
- EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
- incremented for each of the Count operations that is performed. The read or\r
- write operation is performed Count times from the first element of Buffer.\r
-\r
- @param[in] This A pointer to the EFI_CPU_IO_PROTOCOL instance.\r
- @param[in] Width Signifies the width of the I/O or Memory operation.\r
- @param[in] Address The base address of the I/O operation.\r
- @param[in] Count The number of I/O operations to perform. The number of\r
- bytes moved is Width size * Count, starting at Address.\r
- @param[out] Buffer For read operations, the destination buffer to store the results.\r
- For write operations, the source buffer from which to write data.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PI system.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
- and Count is not valid for this PI system.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-CpuMemoryServiceRead (\r
- IN EFI_CPU_IO_PROTOCOL *This,\r
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
- )\r
-{\r
- EFI_STATUS Status;\r
- UINT8 InStride;\r
- UINT8 OutStride;\r
- EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;\r
- UINT8 *Uint8Buffer;\r
-\r
- Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- //\r
- // Select loop based on the width of the transfer\r
- //\r
- InStride = mInStride[Width];\r
- OutStride = mOutStride[Width];\r
- OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
- for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
- if (OperationWidth == EfiCpuIoWidthUint8) {\r
- *Uint8Buffer = MmioRead8 ((UINTN)Address);\r
- } else if (OperationWidth == EfiCpuIoWidthUint16) {\r
- *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);\r
- } else if (OperationWidth == EfiCpuIoWidthUint32) {\r
- *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);\r
- } else if (OperationWidth == EfiCpuIoWidthUint64) {\r
- *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);\r
- }\r
- }\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Writes memory-mapped registers.\r
-\r
- The I/O operations are carried out exactly as requested. The caller is responsible\r
- for satisfying any alignment and I/O width restrictions that a PI System on a\r
- platform might require. For example on some platforms, width requests of\r
- EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
- be handled by the driver.\r
-\r
- If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
- or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
- each of the Count operations that is performed.\r
-\r
- If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
- EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
- incremented for each of the Count operations that is performed. The read or\r
- write operation is performed Count times on the same Address.\r
-\r
- If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
- EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
- incremented for each of the Count operations that is performed. The read or\r
- write operation is performed Count times from the first element of Buffer.\r
-\r
- @param[in] This A pointer to the EFI_CPU_IO_PROTOCOL instance.\r
- @param[in] Width Signifies the width of the I/O or Memory operation.\r
- @param[in] Address The base address of the I/O operation.\r
- @param[in] Count The number of I/O operations to perform. The number of\r
- bytes moved is Width size * Count, starting at Address.\r
- @param[in] Buffer For read operations, the destination buffer to store the results.\r
- For write operations, the source buffer from which to write data.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PI system.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
- and Count is not valid for this PI system.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-CpuMemoryServiceWrite (\r
- IN EFI_CPU_IO_PROTOCOL *This,\r
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- )\r
-{\r
- EFI_STATUS Status;\r
- UINT8 InStride;\r
- UINT8 OutStride;\r
- EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;\r
- UINT8 *Uint8Buffer;\r
-\r
- Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- //\r
- // Select loop based on the width of the transfer\r
- //\r
- InStride = mInStride[Width];\r
- OutStride = mOutStride[Width];\r
- OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
- for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
- if (OperationWidth == EfiCpuIoWidthUint8) {\r
- MmioWrite8 ((UINTN)Address, *Uint8Buffer);\r
- } else if (OperationWidth == EfiCpuIoWidthUint16) {\r
- MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));\r
- } else if (OperationWidth == EfiCpuIoWidthUint32) {\r
- MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));\r
- } else if (OperationWidth == EfiCpuIoWidthUint64) {\r
- MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));\r
- }\r
- }\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Reads I/O registers.\r
-\r
- The I/O operations are carried out exactly as requested. The caller is responsible\r
- for satisfying any alignment and I/O width restrictions that a PI System on a\r
- platform might require. For example on some platforms, width requests of\r
- EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
- be handled by the driver.\r
-\r
- If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
- or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
- each of the Count operations that is performed.\r
-\r
- If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
- EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
- incremented for each of the Count operations that is performed. The read or\r
- write operation is performed Count times on the same Address.\r
-\r
- If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
- EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
- incremented for each of the Count operations that is performed. The read or\r
- write operation is performed Count times from the first element of Buffer.\r
-\r
- @param[in] This A pointer to the EFI_CPU_IO_PROTOCOL instance.\r
- @param[in] Width Signifies the width of the I/O or Memory operation.\r
- @param[in] Address The base address of the I/O operation.\r
- @param[in] Count The number of I/O operations to perform. The number of\r
- bytes moved is Width size * Count, starting at Address.\r
- @param[out] Buffer For read operations, the destination buffer to store the results.\r
- For write operations, the source buffer from which to write data.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PI system.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
- and Count is not valid for this PI system.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-CpuIoServiceRead (\r
- IN EFI_CPU_IO_PROTOCOL *This,\r
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
- )\r
-{\r
- EFI_STATUS Status;\r
- UINT8 InStride;\r
- UINT8 OutStride;\r
- EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;\r
- UINT8 *Uint8Buffer;\r
-\r
- Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- //\r
- // Select loop based on the width of the transfer\r
- //\r
- InStride = mInStride[Width];\r
- OutStride = mOutStride[Width];\r
- OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
-\r
- //\r
- // Fifo operations supported for (mInStride[Width] == 0)\r
- //\r
- if (InStride == 0) {\r
- switch (OperationWidth) {\r
- case EfiCpuIoWidthUint8:\r
- IoReadFifo8 ((UINTN)Address, Count, Buffer);\r
- return EFI_SUCCESS;\r
- case EfiCpuIoWidthUint16:\r
- IoReadFifo16 ((UINTN)Address, Count, Buffer);\r
- return EFI_SUCCESS;\r
- case EfiCpuIoWidthUint32:\r
- IoReadFifo32 ((UINTN)Address, Count, Buffer);\r
- return EFI_SUCCESS;\r
- default:\r
- //\r
- // The CpuIoCheckParameter call above will ensure that this\r
- // path is not taken.\r
- //\r
- ASSERT (FALSE);\r
- break;\r
- }\r
- }\r
-\r
- for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
- if (OperationWidth == EfiCpuIoWidthUint8) {\r
- *Uint8Buffer = IoRead8 ((UINTN)Address);\r
- } else if (OperationWidth == EfiCpuIoWidthUint16) {\r
- *((UINT16 *)Uint8Buffer) = IoRead16 ((UINTN)Address);\r
- } else if (OperationWidth == EfiCpuIoWidthUint32) {\r
- *((UINT32 *)Uint8Buffer) = IoRead32 ((UINTN)Address);\r
- }\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Write I/O registers.\r
-\r
- The I/O operations are carried out exactly as requested. The caller is responsible\r
- for satisfying any alignment and I/O width restrictions that a PI System on a\r
- platform might require. For example on some platforms, width requests of\r
- EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
- be handled by the driver.\r
-\r
- If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
- or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
- each of the Count operations that is performed.\r
-\r
- If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
- EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
- incremented for each of the Count operations that is performed. The read or\r
- write operation is performed Count times on the same Address.\r
-\r
- If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
- EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
- incremented for each of the Count operations that is performed. The read or\r
- write operation is performed Count times from the first element of Buffer.\r
-\r
- @param[in] This A pointer to the EFI_CPU_IO_PROTOCOL instance.\r
- @param[in] Width Signifies the width of the I/O or Memory operation.\r
- @param[in] Address The base address of the I/O operation.\r
- @param[in] Count The number of I/O operations to perform. The number of\r
- bytes moved is Width size * Count, starting at Address.\r
- @param[in] Buffer For read operations, the destination buffer to store the results.\r
- For write operations, the source buffer from which to write data.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PI system.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
- and Count is not valid for this PI system.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-CpuIoServiceWrite (\r
- IN EFI_CPU_IO_PROTOCOL *This,\r
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- )\r
-{\r
- EFI_STATUS Status;\r
- UINT8 InStride;\r
- UINT8 OutStride;\r
- EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;\r
- UINT8 *Uint8Buffer;\r
-\r
- //\r
- // Make sure the parameters are valid\r
- //\r
- Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- //\r
- // Select loop based on the width of the transfer\r
- //\r
- InStride = mInStride[Width];\r
- OutStride = mOutStride[Width];\r
- OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
-\r
- //\r
- // Fifo operations supported for (mInStride[Width] == 0)\r
- //\r
- if (InStride == 0) {\r
- switch (OperationWidth) {\r
- case EfiCpuIoWidthUint8:\r
- IoWriteFifo8 ((UINTN)Address, Count, Buffer);\r
- return EFI_SUCCESS;\r
- case EfiCpuIoWidthUint16:\r
- IoWriteFifo16 ((UINTN)Address, Count, Buffer);\r
- return EFI_SUCCESS;\r
- case EfiCpuIoWidthUint32:\r
- IoWriteFifo32 ((UINTN)Address, Count, Buffer);\r
- return EFI_SUCCESS;\r
- default:\r
- //\r
- // The CpuIoCheckParameter call above will ensure that this\r
- // path is not taken.\r
- //\r
- ASSERT (FALSE);\r
- break;\r
- }\r
- }\r
-\r
- for (Uint8Buffer = (UINT8 *)Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
- if (OperationWidth == EfiCpuIoWidthUint8) {\r
- IoWrite8 ((UINTN)Address, *Uint8Buffer);\r
- } else if (OperationWidth == EfiCpuIoWidthUint16) {\r
- IoWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));\r
- } else if (OperationWidth == EfiCpuIoWidthUint32) {\r
- IoWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));\r
- }\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- The user Entry Point for module CpuIo. The user code starts with this function.\r
-\r
- @param[in] ImageHandle The firmware allocated handle for the EFI image.\r
- @param[in] SystemTable A pointer to the EFI System Table.\r
-\r
- @retval EFI_SUCCESS The entry point is executed successfully.\r
- @retval other Some error occurs when executing this entry point.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-CpuIoInitialize (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
- )\r
-{\r
- EFI_STATUS Status;\r
-\r
- ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIoProtocolGuid);\r
- Status = gBS->InstallMultipleProtocolInterfaces (\r
- &mHandle,\r
- &gEfiCpuIoProtocolGuid, &mCpuIo,\r
- NULL\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- return Status;\r
-}\r
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