the visibility of the SMRAM on the platform. The expectation is\r
that the north bridge or memory controller would publish this protocol. \r
For example, the Memory Controller Hub (MCH) has the hardware provision for this \r
type of control. Because of the protected, distinguished class of memory for IA-32 \r
systems, the expectation is that this protocol would be supported only on IA-32 systems.\r
\r
the visibility of the SMRAM on the platform. The expectation is\r
that the north bridge or memory controller would publish this protocol. \r
For example, the Memory Controller Hub (MCH) has the hardware provision for this \r
type of control. Because of the protected, distinguished class of memory for IA-32 \r
systems, the expectation is that this protocol would be supported only on IA-32 systems.\r
\r