// SMM Access specification Data Structures\r
//\r
typedef struct {\r
- /// \r
- /// Describes the I/O location of the particular port that engendered the synchronous\r
- /// SMI. For example, this location can include but is not limited to the traditional \r
- /// PCAT* APM port of 0B2h.\r
- ///\r
+ /// \r
+ /// Describes the I/O location of the particular port that engendered the synchronous\r
+ /// SMI. For example, this location can include but is not limited to the traditional \r
+ /// PCAT* APM port of 0B2h.\r
+ ///\r
UINT8 SmiTriggerRegister;\r
- ///\r
- /// Describes the value that was written to the respective activation port.\r
- ///\r
+ ///\r
+ /// Describes the value that was written to the respective activation port.\r
+ ///\r
UINT8 SmiDataRegister;\r
} EFI_SMM_CONTROL_REGISTER;\r
\r
@param SmiRegister Pointer to the SMI register description structure\r
\r
@retval EFI_SUCCESS The register structure has been returned.\r
- @retval EFI_DEVICE_ERROR The source could not be cleared.\r
- @retval EFI_INVALID_PARAMETER The service did not support the Periodic input argument.\r
+ @retval EFI_DEVICE_ERROR The source could not be cleared.\r
+ @retval EFI_INVALID_PARAMETER The service did not support the Periodic input argument.\r
\r
**/\r
typedef\r
@param MinimumTriggerPeriod\r
Minimum interval at which the platform can set the period.\r
\r
- @retval EFI_SUCCESS The register structure has been returned.\r
+ @retval EFI_SUCCESS The register structure has been returned.\r
**/\r
\r
//\r
// SMM Control Protocol\r
//\r
/**\r
- This protocol is used initiate SMI/PMI activations. \r
- This protocol could be published by either of the following:\r
- - A processor driver to abstract the SMI/PMI IPI\r
- - The driver that abstracts the ASIC that is supporting the APM port, such as the ICH in an IntelĀ® chipset\r
- Because of the possibility of performing SMI or PMI IPI transactions, the ability to generate this\r
+ This protocol is used initiate SMI/PMI activations. \r
+ This protocol could be published by either of the following:\r
+ - A processor driver to abstract the SMI/PMI IPI\r
+ - The driver that abstracts the ASIC that is supporting the APM port, such as the ICH in an IntelĀ® chipset\r
+ Because of the possibility of performing SMI or PMI IPI transactions, the ability to generate this\r
\r
- The EFI_SMM_CONTROL_PROTOCOL is used by the platform chipset or processor driver. This\r
+ The EFI_SMM_CONTROL_PROTOCOL is used by the platform chipset or processor driver. This\r
protocol is useable both in boot services and runtime. The runtime aspect is so that an\r
implementation of EFI_SMM_BASE_PROTOCOL.Communicate() can layer upon this service\r
and provide an SMI callback from a general EFI runtime driver.\r
SMI or PMI. There are often I/O ports that, when accessed, will engender the\r
**/\r
struct _EFI_SMM_CONTROL_PROTOCOL {\r
- ///\r
- /// Initiates the SMI/PMI activation.\r
- ///\r
+ ///\r
+ /// Initiates the SMI/PMI activation.\r
+ ///\r
EFI_SMM_ACTIVATE Trigger;\r
- ///\r
- /// Quiesces the SMI/PMI activation.\r
- ///\r
+ ///\r
+ /// Quiesces the SMI/PMI activation.\r
+ ///\r
EFI_SMM_DEACTIVATE Clear;\r
- ///\r
- /// Provides data on the register used as the source of the SMI.\r
- ///\r
+ ///\r
+ /// Provides data on the register used as the source of the SMI.\r
+ ///\r
EFI_SMM_GET_REGISTER_INFO GetRegisterInfo;\r
- ///\r
- /// Minimum interval at which the platform can set the period. A maximum is not\r
- /// specified in that the SMM infrastructure code can emulate a maximum interval that is\r
- /// greater than the hardware capabilities by using software emulation in the SMM\r
- /// infrastructure code.\r
- ///\r
+ ///\r
+ /// Minimum interval at which the platform can set the period. A maximum is not\r
+ /// specified in that the SMM infrastructure code can emulate a maximum interval that is\r
+ /// greater than the hardware capabilities by using software emulation in the SMM\r
+ /// infrastructure code.\r
+ ///\r
UINTN MinimumTriggerPeriod;\r
};\r
\r