+//\r
+// SMM Control Protocol\r
+//\r
+/**\r
+ This protocol is used to initiate SMI/PMI activations. \r
+ This protocol could be published by either:\r
+ - A processor driver to abstract the SMI/PMI IPI.\r
+ - The driver that abstracts the ASIC that is supporting the APM port, such as the ICH in an Intel chipset.\r
+ Because of the possibility of performing SMI or PMI IPI transactions, the ability to generate this.\r
+ \r
+ The EFI_SMM_CONTROL_PROTOCOL is used by the platform chipset or processor driver. This\r
+ protocol is usable both in boot services and at runtime. The runtime aspect enables an\r
+ implementation of EFI_SMM_BASE_PROTOCOL.Communicate() to layer upon this service\r
+ and provide an SMI callback from a general EFI runtime driver.\r
+ This protocol provides an abstraction to the platform hardware that generates an\r
+ SMI or PMI. There are often I/O ports that, when accessed, will engender the SMI or PMI.\r
+ Also, this hardware optionally supports the periodic genearation of these signals.\r
+\r
+**/\r