IntelFsp2Pkg: Support Multi-Phase SiInit and debug handlers.

[mirror_edk2.git] / IntelFsp2Pkg / FspSecCore / Fsp22SecCoreS.inf

diff --git a/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf b/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf
new file mode 100644 (file)
index 0000000..0a24eb2
--- /dev/null
+++ b/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf
@@ -0,0 +1,52 @@
+## @file\r
+#  Sec Core for FSP to support MultiPhase (SeparatePhase) SiInitialization.\r
+#\r
+#  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>\r
+#\r
+#  SPDX-License-Identifier: BSD-2-Clause-Patent\r
+#\r
+##\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = Fsp22SecCoreS\r
+  FILE_GUID                      = DF0FCD70-264A-40BF-BBD4-06C76DB19CB1\r
+  MODULE_TYPE                    = SEC\r
+  VERSION_STRING                 = 1.0\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32\r
+#\r
+\r
+[Sources]\r
+  SecFspApiChk.c\r
+  SecFsp.h\r
+\r
+[Sources.IA32]\r
+  Ia32/Stack.nasm\r
+  Ia32/Fsp22ApiEntryS.nasm\r
+  Ia32/FspApiEntryCommon.nasm\r
+  Ia32/FspHelper.nasm\r
+\r
+[Binaries.Ia32]\r
+  RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  IntelFsp2Pkg/IntelFsp2Pkg.dec\r
+\r
+[LibraryClasses]\r
+  BaseMemoryLib\r
+  DebugLib\r
+  BaseLib\r
+  PciCf8Lib\r
+  SerialPortLib\r
+  FspSwitchStackLib\r
+  FspCommonLib\r
+  FspSecPlatformLib\r
+\r
+[Ppis]\r
+  gEfiTemporaryRamSupportPpiGuid                              ## PRODUCES\r
+\r