UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm

[mirror_edk2.git] / IntelFsp2Pkg / Include / FspStatusCode.h

diff --git a/IntelFsp2Pkg/Include/FspStatusCode.h b/IntelFsp2Pkg/Include/FspStatusCode.h
index c9a316e6e75257d06df74953a67f88961ba16030..e294aa343565d9ebb6b2872cb987b178b9a94737 100644 (file)
--- a/IntelFsp2Pkg/Include/FspStatusCode.h
+++ b/IntelFsp2Pkg/Include/FspStatusCode.h
@@ -2,13 +2,7 @@
   Intel FSP status code definition\r
 \r
   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
-  This program and the accompanying materials\r
-  are licensed and made available under the terms and conditions of the BSD License\r
-  which accompanies this distribution.  The full text of the license may be found at\r
-  http://opensource.org/licenses/bsd-license.php.\r
-\r
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
 \r
@@ -18,29 +12,29 @@
 //\r
 // FSP API - 4 BITS\r
 //\r
-#define FSP_STATUS_CODE_TEMP_RAM_INIT                0xF000\r
-#define FSP_STATUS_CODE_MEMORY_INIT                  0xD000\r
-#define FSP_STATUS_CODE_TEMP_RAM_EXIT                0xB000\r
-#define FSP_STATUS_CODE_SILICON_INIT                 0x9000\r
-#define FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION  0x6000\r
-#define FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION   0x4000\r
-#define FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION 0x2000\r
+#define FSP_STATUS_CODE_TEMP_RAM_INIT                 0xF000\r
+#define FSP_STATUS_CODE_MEMORY_INIT                   0xD000\r
+#define FSP_STATUS_CODE_TEMP_RAM_EXIT                 0xB000\r
+#define FSP_STATUS_CODE_SILICON_INIT                  0x9000\r
+#define FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION   0x6000\r
+#define FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION    0x4000\r
+#define FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION  0x2000\r
 \r
 //\r
 // MODULE - 4 BITS\r
 //\r
-#define FSP_STATUS_CODE_GFX_PEIM                     0x0700\r
-#define FSP_STATUS_CODE_COMMON_CODE                  0x0800\r
-#define FSP_STATUS_CODE_SILICON_COMMON_CODE          0x0900\r
-#define FSP_STATUS_CODE_SYSTEM_AGENT                 0x0A00\r
-#define FSP_STATUS_CODE_PCH                          0x0B00\r
-#define FSP_STATUS_CODE_CPU                          0x0C00\r
-#define FSP_STATUS_CODE_MRC                          0x0D00\r
-#define FSP_STATUS_CODE_ME_BIOS                      0x0E00\r
+#define FSP_STATUS_CODE_GFX_PEIM             0x0700\r
+#define FSP_STATUS_CODE_COMMON_CODE          0x0800\r
+#define FSP_STATUS_CODE_SILICON_COMMON_CODE  0x0900\r
+#define FSP_STATUS_CODE_SYSTEM_AGENT         0x0A00\r
+#define FSP_STATUS_CODE_PCH                  0x0B00\r
+#define FSP_STATUS_CODE_CPU                  0x0C00\r
+#define FSP_STATUS_CODE_MRC                  0x0D00\r
+#define FSP_STATUS_CODE_ME_BIOS              0x0E00\r
 //\r
 // Individual Codes - 1 BYTE\r
 //\r
-#define FSP_STATUS_CODE_API_ENTRY                    0x0000\r
-#define FSP_STATUS_CODE_API_EXIT                     0x007F\r
+#define FSP_STATUS_CODE_API_ENTRY  0x0000\r
+#define FSP_STATUS_CODE_API_EXIT   0x007F\r
 \r
 #endif\r