UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm

[mirror_edk2.git] / IntelFsp2Pkg / IntelFsp2Pkg.dec

diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dec b/IntelFsp2Pkg/IntelFsp2Pkg.dec
index 64a31b350539a15dadff87da96e17a66bef9bae8..d1c3d3ee7b90bf83c86ff21c9a7a0c58883cd537 100644 (file)
--- a/IntelFsp2Pkg/IntelFsp2Pkg.dec
+++ b/IntelFsp2Pkg/IntelFsp2Pkg.dec
@@ -1,14 +1,8 @@
 ## @file\r
 # Provides driver and definitions to build fsp in EDKII bios.\r
 #\r
-# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials are licensed and made available under\r
-# the terms and conditions of the BSD License that accompanies this distribution.\r
-# The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+# Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
 #\r
 ##\r
 \r
@@ -43,18 +37,37 @@
   ##  @libraryclass  Provides FSP platform sec related actions.\r
   FspSecPlatformLib|Include/Library/FspSecPlatformLib.h\r
 \r
+  ## @libraryclass  Provides FSP MultiPhase service functions.\r
+  FspMultiPhaseLib|Include/Library/FspMultiPhaseLib.h\r
+\r
 [Ppis]\r
   #\r
   # PPI to indicate FSP is ready to enter notify phase\r
   # This provides flexibility for any late initialization that must be done right before entering notify phase.\r
   #\r
-  gFspReadyForNotifyPhasePpiGuid        = { 0xcd167c1e, 0x6e0b, 0x42b3, { 0x82, 0xf6, 0xe3, 0xe9, 0x6, 0x19, 0x98, 0x10}}\r
+  gFspReadyForNotifyPhasePpiGuid        = { 0xcd167c1e, 0x6e0b, 0x42b3, {0x82, 0xf6, 0xe3, 0xe9, 0x06, 0x19, 0x98, 0x10}}\r
 \r
   #\r
   # PPI as dependency on some modules which only required for API mode\r
   #\r
   gFspInApiModePpiGuid                  = { 0xa1eeab87, 0xc859, 0x479d, {0x89, 0xb5, 0x14, 0x61, 0xf4, 0x06, 0x1a, 0x3e}}\r
 \r
+  #\r
+  # PPI for Architectural configuration data for FSP-M\r
+  #\r
+  gFspmArchConfigPpiGuid                = { 0x824d5a3a, 0xaf92, 0x4c0c, {0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb}}\r
+\r
+  #\r
+  # PPI to tear down the temporary memory set up by TempRamInit ().\r
+  #\r
+  gFspTempRamExitPpiGuid                = { 0xbc1cfbdb, 0x7e50, 0x42be, {0xb4, 0x87, 0x22, 0xe0, 0xa9, 0x0c, 0xb0, 0x52}}\r
+\r
+  #\r
+  # PPI for Variable Services\r
+  #\r
+  gEdkiiPeiVariablePpiGuid              = { 0xe7b2cd04, 0x4b14, 0x44c2, {0xb7, 0x48, 0xce, 0xaf, 0x2b, 0x66, 0x4a, 0xb0}}\r
+\r
+\r
 [Guids]\r
   #\r
   # GUID defined in package\r
@@ -64,15 +77,13 @@
   # Guid define in FSP EAS\r
   gFspHeaderFileGuid                    = { 0x912740BE, 0x2284, 0x4734, { 0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C } }\r
   gFspReservedMemoryResourceHobGuid     = { 0x69a79759, 0x1373, 0x4367, { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } }\r
+  gFspNonVolatileStorageHob2Guid        = { 0x4866788f, 0x6ba8, 0x47d8, { 0x83, 0x06, 0xac, 0xf7, 0x7f, 0x55, 0x10, 0x46 } }\r
   gFspNonVolatileStorageHobGuid         = { 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 } }\r
   gFspBootLoaderTolumHobGuid            = { 0x73ff4f56, 0xaa8e, 0x4451, { 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44 } } # FSP EAS v1.1\r
 \r
   gFspPerformanceDataGuid               = { 0x56ed21b6, 0xba23, 0x429e, { 0x89, 0x32, 0x37, 0x6d, 0x8e, 0x18, 0x2e, 0xe3 } }\r
   gFspEventEndOfFirmwareGuid            = { 0xbd44f629, 0xeae7, 0x4198, { 0x87, 0xf1, 0x39, 0xfa, 0xb0, 0xfd, 0x71, 0x7e } }\r
 \r
-[Ppis]\r
-  gFspmArchConfigPpiGuid                = { 0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb } }\r
-\r
 [PcdsFixedAtBuild]\r
   gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress |0xFED00108|UINT32|0x00000001\r
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase         |0xFEF00000|UINT32|0x10001001\r
@@ -86,14 +97,28 @@
   gIntelFsp2PkgTokenSpaceGuid.PcdFspBootFirmwareVolumeBase|0xFFF80000|UINT32|0x10000003\r
   gIntelFsp2PkgTokenSpaceGuid.PcdFspHeaderSpecVersion     |      0x20| UINT8|0x00000002\r
 \r
+  #\r
   # x % of FSP temporary memory will be used for heap\r
   # (100 - x) % of FSP temporary memory will be used for stack\r
+  # 0 means FSP will share the stack with boot loader and FSP temporary memory is heap\r
+  #   Note: This mode assumes boot loader stack is large enough for FSP to use.\r
+  #\r
   gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage    |        50| UINT8|0x10000004\r
   #\r
   # Maximal Interrupt supported in IDT table.\r
   #\r
   gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported |        34| UINT8|0x10000005\r
+  #\r
+  # Allows FSP-M to reserve a section of Temporary RAM for implementation specific use.\r
+  # Reduces the amount of memory available for the PeiCore heap.\r
+  #\r
+  gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize |0x00000000|UINT32|0x10000006\r
 \r
 [PcdsFixedAtBuild,PcdsDynamic,PcdsDynamicEx]\r
-  gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedMemoryLength |0x00100000|UINT32|0x46530000\r
-  gIntelFsp2PkgTokenSpaceGuid.PcdBootLoaderEntry         |0xFFFFFFE4|UINT32|0x46530100\r
+  gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedMemoryLength  |0x00100000|UINT32|0x46530000\r
+  gIntelFsp2PkgTokenSpaceGuid.PcdBootLoaderEntry          |0xFFFFFFE4|UINT32|0x46530100\r
+  #\r
+  # Different FSP Components may have different NumberOfPhases which can be defined\r
+  # by each FspSecCore module from DSC.\r
+  #\r
+  gIntelFsp2PkgTokenSpaceGuid.PcdMultiPhaseNumberOfPhases |0x00000000|UINT32|0x46530101\r