UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm

[mirror_edk2.git] / IntelFsp2Pkg / Tools / SplitFspBin.py

diff --git a/IntelFsp2Pkg/Tools/SplitFspBin.py b/IntelFsp2Pkg/Tools/SplitFspBin.py
index 317d9c1fa0e4314fe827ceb8fdfa21395c72e529..419e5ba9850ef42057c43dfa549fa59d434c2b1c 100644 (file)
--- a/IntelFsp2Pkg/Tools/SplitFspBin.py
+++ b/IntelFsp2Pkg/Tools/SplitFspBin.py
@@ -103,29 +103,31 @@ class FSP_COMMON_HEADER(Structure):
 \r
 class FSP_INFORMATION_HEADER(Structure):\r
      _fields_ = [\r
-        ('Signature',                      ARRAY(c_char, 4)),\r
-        ('HeaderLength',                   c_uint32),\r
-        ('Reserved1',                      c_uint16),\r
-        ('SpecVersion',                    c_uint8),\r
-        ('HeaderRevision',                 c_uint8),\r
-        ('ImageRevision',                  c_uint32),\r
-        ('ImageId',                        ARRAY(c_char, 8)),\r
-        ('ImageSize',                      c_uint32),\r
-        ('ImageBase',                      c_uint32),\r
-        ('ImageAttribute',                 c_uint16),\r
-        ('ComponentAttribute',             c_uint16),\r
-        ('CfgRegionOffset',                c_uint32),\r
-        ('CfgRegionSize',                  c_uint32),\r
-        ('Reserved2',                      c_uint32),\r
-        ('TempRamInitEntryOffset',         c_uint32),\r
-        ('Reserved3',                      c_uint32),\r
-        ('NotifyPhaseEntryOffset',         c_uint32),\r
-        ('FspMemoryInitEntryOffset',       c_uint32),\r
-        ('TempRamExitEntryOffset',         c_uint32),\r
-        ('FspSiliconInitEntryOffset',      c_uint32),\r
-        ('FspMultiPhaseSiInitEntryOffset', c_uint32),\r
-        ('ExtendedImageRevision',          c_uint16),\r
-        ('Reserved4',                      c_uint16)\r
+        ('Signature',                       ARRAY(c_char, 4)),\r
+        ('HeaderLength',                    c_uint32),\r
+        ('Reserved1',                       c_uint16),\r
+        ('SpecVersion',                     c_uint8),\r
+        ('HeaderRevision',                  c_uint8),\r
+        ('ImageRevision',                   c_uint32),\r
+        ('ImageId',                         ARRAY(c_char, 8)),\r
+        ('ImageSize',                       c_uint32),\r
+        ('ImageBase',                       c_uint32),\r
+        ('ImageAttribute',                  c_uint16),\r
+        ('ComponentAttribute',              c_uint16),\r
+        ('CfgRegionOffset',                 c_uint32),\r
+        ('CfgRegionSize',                   c_uint32),\r
+        ('Reserved2',                       c_uint32),\r
+        ('TempRamInitEntryOffset',          c_uint32),\r
+        ('Reserved3',                       c_uint32),\r
+        ('NotifyPhaseEntryOffset',          c_uint32),\r
+        ('FspMemoryInitEntryOffset',        c_uint32),\r
+        ('TempRamExitEntryOffset',          c_uint32),\r
+        ('FspSiliconInitEntryOffset',       c_uint32),\r
+        ('FspMultiPhaseSiInitEntryOffset',  c_uint32),\r
+        ('ExtendedImageRevision',           c_uint16),\r
+        ('Reserved4',                       c_uint16),\r
+        ('FspMultiPhaseMemInitEntryOffset', c_uint32),\r
+        ('FspSmmInitEntryOffset',           c_uint32)\r
     ]\r
 \r
 class FSP_PATCH_TABLE(Structure):\r
@@ -492,7 +494,7 @@ class FspImage:
         self.FihOffset = fihoff\r
         self.Offset    = offset\r
         self.FvIdxList = []\r
-        self.Type      = "XTMSIXXXXOXXXXXXX"[(fih.ComponentAttribute >> 12) & 0x0F]\r
+        self.Type      = "XTMSIXXXOXXXXXXX"[(fih.ComponentAttribute >> 12) & 0x0F]\r
         self.PatchList = patch\r
         self.PatchList.append(fihoff + 0x1C)\r
 \r