-;------------------------------------------------------------------------------\r
+;; @file\r
+; Provide FSP API entry points.\r
;\r
-; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
;\r
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-; Abstract:\r
-;\r
-; Provide FSP API entry points.\r
-;\r
-;------------------------------------------------------------------------------\r
+;;\r
\r
.586p\r
.model flat,C\r
.xmm\r
\r
INCLUDE SaveRestoreSse.inc\r
-INCLUDE UcodeLoad.inc\r
+INCLUDE MicrocodeLoad.inc\r
\r
;\r
; Following are fixed PCDs\r
EXTERN PcdGet32(PcdTemporaryRamBase):DWORD\r
EXTERN PcdGet32(PcdTemporaryRamSize):DWORD\r
EXTERN PcdGet32(PcdFspTemporaryRamSize):DWORD\r
+EXTERN PcdGet32(PcdFspAreaSize):DWORD\r
\r
;\r
; Following functions will be provided in C\r
;\r
-EXTERN FspImageSizeOffset:DWORD\r
+\r
EXTERN SecStartup:PROC\r
EXTERN FspApiCallingCheck:PROC\r
\r
;\r
; Following functions will be provided in PlatformSecLib\r
;\r
-EXTERN GetFspBaseAddress:PROC\r
+EXTERN AsmGetFspBaseAddress:PROC\r
+EXTERN AsmGetFspInfoHeader:PROC\r
EXTERN GetBootFirmwareVolumeOffset:PROC\r
-EXTERN PlatformTempRamInit:PROC\r
-EXTERN Pei2LoaderSwitchStack:PROC\r
-EXTERN FspSelfCheck(FspSelfCheckDflt):PROC\r
-EXTERN PlatformBasicInit(PlatformBasicInitDflt):PROC\r
-EXTERN LoadUcode(LoadUcodeDflt):PROC\r
+EXTERN Loader2PeiSwitchStack:PROC\r
+EXTERN LoadMicrocode(LoadMicrocodeDefault):PROC\r
+EXTERN SecPlatformInit(SecPlatformInitDefault):PROC\r
+EXTERN SecCarInit:PROC\r
\r
;\r
; Define the data length that we saved on the stack top\r
DATA_LEN_OF_MCUD EQU 18h\r
DATA_LEN_AT_STACK_TOP EQU (DATA_LEN_OF_PER0 + DATA_LEN_OF_MCUD + 4)\r
\r
-;------------------------------------------------------------------------------\r
-FspSelfCheckDflt PROC NEAR PUBLIC\r
- ; Inputs:\r
- ; eax -> Return address\r
- ; Outputs:\r
- ; eax -> 0 - Successful, Non-zero - Failed.\r
- ; Register Usage:\r
- ; eax is cleared and ebp is used for return address.\r
- ; All others reserved.\r
-\r
- ; Save return address to EBP\r
- mov ebp, eax\r
-\r
- xor eax, eax\r
-exit:\r
- jmp ebp\r
-FspSelfCheckDflt ENDP\r
+;\r
+; Define SSE macros\r
+;\r
+LOAD_MMX_EXT MACRO ReturnAddress, MmxRegister\r
+ mov esi, ReturnAddress\r
+ movd MmxRegister, esi ; save ReturnAddress into MMX\r
+ENDM\r
+\r
+CALL_MMX_EXT MACRO RoutineLabel, MmxRegister\r
+ local ReturnAddress\r
+ mov esi, offset ReturnAddress\r
+ movd MmxRegister, esi ; save ReturnAddress into MMX\r
+ jmp RoutineLabel\r
+ReturnAddress:\r
+ENDM\r
+\r
+RET_ESI_EXT MACRO MmxRegister\r
+ movd esi, MmxRegister ; move ReturnAddress from MMX to ESI\r
+ jmp esi\r
+ENDM\r
+\r
+CALL_MMX MACRO RoutineLabel\r
+ CALL_MMX_EXT RoutineLabel, mm7\r
+ENDM\r
+\r
+RET_ESI MACRO\r
+ RET_ESI_EXT mm7\r
+ENDM\r
\r
;------------------------------------------------------------------------------\r
-PlatformBasicInitDflt PROC NEAR PUBLIC\r
+SecPlatformInitDefault PROC NEAR PUBLIC\r
; Inputs:\r
- ; eax -> Return address\r
+ ; mm7 -> Return address\r
; Outputs:\r
; eax -> 0 - Successful, Non-zero - Failed.\r
; Register Usage:\r
; eax is cleared and ebp is used for return address.\r
; All others reserved.\r
-\r
+ \r
; Save return address to EBP\r
- mov ebp, eax\r
+ movd ebp, mm7\r
\r
xor eax, eax\r
exit:\r
jmp ebp\r
-PlatformBasicInitDflt ENDP\r
+SecPlatformInitDefault ENDP\r
\r
;------------------------------------------------------------------------------\r
-LoadUcodeDflt PROC NEAR PUBLIC\r
+LoadMicrocodeDefault PROC NEAR PUBLIC\r
; Inputs:\r
- ; esp -> LOAD_UCODE_PARAMS pointer\r
+ ; esp -> LoadMicrocodeParams pointer\r
; Register Usage:\r
; esp Preserved\r
; All others destroyed\r
;\r
;\r
; Save return address to EBP\r
- mov ebp, eax\r
+ movd ebp, mm7\r
\r
cmp esp, 0\r
jz paramerror\r
- mov eax, dword ptr [esp] ; Parameter pointer\r
+ mov eax, dword ptr [esp + 4] ; Parameter pointer\r
cmp eax, 0\r
jz paramerror\r
mov esp, eax\r
- mov esi, [esp].LOAD_UCODE_PARAMS.ucode_code_addr\r
+ mov esi, [esp].LoadMicrocodeParams.MicrocodeCodeAddr\r
cmp esi, 0\r
jnz check_main_header\r
\r
mov eax, 080000002h\r
jmp exit\r
\r
- mov esi, [esp].LOAD_UCODE_PARAMS.ucode_code_addr\r
+ mov esi, [esp].LoadMicrocodeParams.MicrocodeCodeAddr\r
\r
check_main_header:\r
; Get processor signature and platform ID from the installed processor\r
; Check for valid microcode header\r
; Minimal test checking for header version and loader version as 1\r
mov eax, dword ptr 1\r
- cmp [esi].ucode_hdr.version, eax\r
+ cmp [esi].MicrocodeHdr.MicrocodeHdrVersion, eax\r
jne advance_fixed_size\r
- cmp [esi].ucode_hdr.loader, eax\r
+ cmp [esi].MicrocodeHdr.MicrocodeHdrLoader, eax\r
jne advance_fixed_size\r
\r
; Check if signature and plaform ID match\r
- cmp ebx, [esi].ucode_hdr.processor\r
+ cmp ebx, [esi].MicrocodeHdr.MicrocodeHdrProcessor\r
jne @f\r
- test edx, [esi].ucode_hdr.flags\r
+ test edx, [esi].MicrocodeHdr.MicrocodeHdrFlags\r
jnz load_check ; Jif signature and platform ID match\r
\r
@@:\r
; Check if extended header exists\r
- ; First check if total_size and data_size are valid\r
+ ; First check if MicrocodeHdrTotalSize and MicrocodeHdrDataSize are valid\r
xor eax, eax\r
- cmp [esi].ucode_hdr.total_size, eax\r
+ cmp [esi].MicrocodeHdr.MicrocodeHdrTotalSize, eax\r
je next_microcode\r
- cmp [esi].ucode_hdr.data_size, eax\r
+ cmp [esi].MicrocodeHdr.MicrocodeHdrDataSize, eax\r
je next_microcode\r
\r
; Then verify total size - sizeof header > data size\r
- mov ecx, [esi].ucode_hdr.total_size\r
- sub ecx, sizeof ucode_hdr\r
- cmp ecx, [esi].ucode_hdr.data_size\r
+ mov ecx, [esi].MicrocodeHdr.MicrocodeHdrTotalSize\r
+ sub ecx, sizeof MicrocodeHdr\r
+ cmp ecx, [esi].MicrocodeHdr.MicrocodeHdrDataSize\r
jng next_microcode ; Jif extended header does not exist\r
\r
; Set edi -> extended header\r
mov edi, esi\r
- add edi, sizeof ucode_hdr\r
- add edi, [esi].ucode_hdr.data_size\r
+ add edi, sizeof MicrocodeHdr\r
+ add edi, [esi].MicrocodeHdr.MicrocodeHdrDataSize\r
\r
; Get count of extended structures\r
- mov ecx, [edi].ext_sig_hdr.count\r
+ mov ecx, [edi].ExtSigHdr.ExtSigHdrCount\r
\r
; Move pointer to first signature structure\r
- add edi, sizeof ext_sig_hdr\r
+ add edi, sizeof ExtSigHdr\r
\r
check_ext_sig:\r
; Check if extended signature and platform ID match\r
- cmp [edi].ext_sig.processor, ebx\r
+ cmp [edi].ExtSig.ExtSigProcessor, ebx\r
jne @f\r
- test [edi].ext_sig.flags, edx\r
+ test [edi].ExtSig.ExtSigFlags, edx\r
jnz load_check ; Jif signature and platform ID match\r
@@:\r
; Check if any more extended signatures exist\r
- add edi, sizeof ext_sig\r
+ add edi, sizeof ExtSig\r
loop check_ext_sig\r
\r
next_microcode:\r
; Advance just after end of this microcode\r
xor eax, eax\r
- cmp [esi].ucode_hdr.total_size, eax\r
+ cmp [esi].MicrocodeHdr.MicrocodeHdrTotalSize, eax\r
je @f\r
- add esi, [esi].ucode_hdr.total_size\r
+ add esi, [esi].MicrocodeHdr.MicrocodeHdrTotalSize\r
jmp check_address\r
@@:\r
add esi, dword ptr 2048\r
\r
check_address:\r
; Is valid Microcode start point ?\r
- cmp dword ptr [esi], 0ffffffffh\r
+ cmp dword ptr [esi].MicrocodeHdr.MicrocodeHdrVersion, 0ffffffffh\r
jz done\r
\r
+ ; Is automatic size detection ?\r
+ mov eax, [esp].LoadMicrocodeParams.MicrocodeCodeSize\r
+ cmp eax, 0ffffffffh\r
+ jz @f\r
+\r
; Address >= microcode region address + microcode region size?\r
- mov eax, [esp].LOAD_UCODE_PARAMS.ucode_code_addr\r
- add eax, [esp].LOAD_UCODE_PARAMS.ucode_code_size\r
+ add eax, [esp].LoadMicrocodeParams.MicrocodeCodeAddr\r
cmp esi, eax\r
- jae done ;Jif address is outside of ucode region\r
+ jae done ;Jif address is outside of microcode region\r
jmp check_main_header\r
\r
+@@:\r
load_check:\r
; Get the revision of the current microcode update loaded\r
mov ecx, MSR_IA32_BIOS_SIGN_ID\r
rdmsr ; Get current microcode signature\r
\r
; Verify this microcode update is not already loaded\r
- cmp [esi].ucode_hdr.revision, edx\r
+ cmp [esi].MicrocodeHdr.MicrocodeHdrRevision, edx\r
je continue\r
\r
load_microcode:\r
; ECX contains 79h (IA32_BIOS_UPDT_TRIG)\r
; Start microcode load with wrmsr\r
mov eax, esi\r
- add eax, sizeof ucode_hdr\r
+ add eax, sizeof MicrocodeHdr\r
xor edx, edx\r
mov ecx, MSR_IA32_BIOS_UPDT_TRIG\r
wrmsr\r
exit:\r
jmp ebp\r
\r
-LoadUcodeDflt ENDP\r
+LoadMicrocodeDefault ENDP\r
+\r
+EstablishStackFsp PROC NEAR PRIVATE\r
+ ;\r
+ ; Save parameter pointer in edx\r
+ ;\r
+ mov edx, dword ptr [esp + 4]\r
+\r
+ ;\r
+ ; Enable FSP STACK\r
+ ;\r
+ mov esp, PcdGet32 (PcdTemporaryRamBase)\r
+ add esp, PcdGet32 (PcdTemporaryRamSize)\r
+\r
+ push DATA_LEN_OF_MCUD ; Size of the data region\r
+ push 4455434Dh ; Signature of the data region 'MCUD'\r
+ push dword ptr [edx + 12] ; Code size\r
+ push dword ptr [edx + 8] ; Code base\r
+ push dword ptr [edx + 4] ; Microcode size\r
+ push dword ptr [edx] ; Microcode base\r
+\r
+ ;\r
+ ; Save API entry/exit timestamp into stack\r
+ ;\r
+ push DATA_LEN_OF_PER0 ; Size of the data region \r
+ push 30524550h ; Signature of the data region 'PER0'\r
+ LOAD_EDX\r
+ push edx\r
+ LOAD_EAX\r
+ push eax\r
+ rdtsc\r
+ push edx\r
+ push eax\r
+\r
+ ;\r
+ ; Terminator for the data on stack\r
+ ; \r
+ push 0\r
+\r
+ ;\r
+ ; Set ECX/EDX to the BootLoader temporary memory range\r
+ ;\r
+ mov ecx, PcdGet32 (PcdTemporaryRamBase)\r
+ mov edx, ecx\r
+ add edx, PcdGet32 (PcdTemporaryRamSize)\r
+ sub edx, PcdGet32 (PcdFspTemporaryRamSize)\r
+\r
+ xor eax, eax\r
+\r
+ RET_ESI\r
+\r
+EstablishStackFsp ENDP\r
+\r
\r
;----------------------------------------------------------------------------\r
; TempRamInit API\r
SAVE_REGS\r
\r
;\r
- ; Save timestamp into XMM4 & XMM5\r
+ ; Save timestamp into XMM6\r
;\r
rdtsc\r
SAVE_EAX\r
jz NemInitExit\r
\r
;\r
- ; CPUID/DeviceID check\r
+ ; Sec Platform Init\r
;\r
- mov eax, @F\r
- jmp FspSelfCheck ; Note: ESP can not be changed.\r
-@@:\r
+ CALL_MMX SecPlatformInit\r
cmp eax, 0\r
jnz NemInitExit\r
-\r
- ;\r
- ; Platform Basic Init.\r
- ;\r
- mov eax, @F\r
- jmp PlatformBasicInit\r
-@@:\r
- cmp eax, 0\r
- jnz NemInitExit\r
-\r
- ;\r
+ \r
; Load microcode\r
- ;\r
- mov eax, @F\r
- add esp, 4\r
- jmp LoadUcode\r
-@@:\r
LOAD_ESP\r
- cmp eax, 0\r
- jnz NemInitExit\r
+ CALL_MMX LoadMicrocode\r
+ SXMMN xmm6, 3, eax ;Save microcode return status in ECX-SLOT 3 in xmm6.\r
+ ;@note If return value eax is not 0, microcode did not load, but continue and attempt to boot.\r
\r
- ;\r
- ; Call platform NEM init\r
- ;\r
- mov eax, @F\r
- add esp, 4\r
- jmp PlatformTempRamInit\r
-@@:\r
+ ; Call Sec CAR Init\r
LOAD_ESP\r
+ CALL_MMX SecCarInit\r
cmp eax, 0\r
jnz NemInitExit\r
\r
- ;\r
- ; Save parameter pointer in edx\r
- ;\r
- mov edx, dword ptr [esp + 4]\r
-\r
- ;\r
- ; Enable FSP STACK\r
- ;\r
- mov esp, PcdGet32(PcdTemporaryRamBase)\r
- add esp, PcdGet32(PcdTemporaryRamSize)\r
-\r
- push DATA_LEN_OF_MCUD ; Size of the data region\r
- push 4455434Dh ; Signature of the data region 'MCUD'\r
- push dword ptr [edx + 4] ; Microcode size\r
- push dword ptr [edx + 0] ; Microcode base\r
- push dword ptr [edx + 12] ; Code size\r
- push dword ptr [edx + 8] ; Code base\r
-\r
- ;\r
- ; Save API entry/exit timestamp into stack\r
- ;\r
- push DATA_LEN_OF_PER0 ; Size of the data region\r
- push 30524550h ; Signature of the data region 'PER0'\r
- rdtsc\r
- push edx\r
- push eax\r
- LOAD_EAX\r
- LOAD_EDX\r
- push edx\r
- push eax\r
-\r
- ;\r
- ; Terminator for the data on stack\r
- ;\r
- push 0\r
-\r
- ;\r
- ; Set ECX/EDX to the bootloader temporary memory range\r
- ;\r
- mov ecx, PcdGet32(PcdTemporaryRamBase)\r
- mov edx, ecx\r
- add edx, PcdGet32(PcdTemporaryRamSize)\r
- sub edx, PcdGet32(PcdFspTemporaryRamSize)\r
+ LOAD_ESP\r
+ CALL_MMX EstablishStackFsp\r
\r
- xor eax, eax\r
+ LXMMN xmm6, eax, 3 ;Restore microcode status if no CAR init error from ECX-SLOT 3 in xmm6.\r
\r
NemInitExit:\r
;\r
;\r
;----------------------------------------------------------------------------\r
FspInitApi PROC NEAR PUBLIC\r
+ mov eax, 1\r
+ jmp FspApiCommon\r
+ FspInitApi ENDP\r
+\r
+;----------------------------------------------------------------------------\r
+; NotifyPhase API\r
+;\r
+; This FSP API will notify the FSP about the different phases in the boot\r
+; process\r
+;\r
+;----------------------------------------------------------------------------\r
+NotifyPhaseApi PROC C PUBLIC\r
+ mov eax, 2\r
+ jmp FspApiCommon\r
+NotifyPhaseApi ENDP\r
+\r
+;----------------------------------------------------------------------------\r
+; FspMemoryInit API\r
+;\r
+; This FSP API is called after TempRamInit and initializes the memory.\r
+;\r
+;----------------------------------------------------------------------------\r
+FspMemoryInitApi PROC NEAR PUBLIC\r
+ mov eax, 3\r
+ jmp FspApiCommon\r
+FspMemoryInitApi ENDP\r
+\r
+\r
+;----------------------------------------------------------------------------\r
+; TempRamExitApi API\r
+;\r
+; This API tears down temporary RAM\r
+;\r
+;----------------------------------------------------------------------------\r
+TempRamExitApi PROC C PUBLIC\r
+ mov eax, 4\r
+ jmp FspApiCommon\r
+TempRamExitApi ENDP\r
+\r
+\r
+;----------------------------------------------------------------------------\r
+; FspSiliconInit API\r
+;\r
+; This FSP API initializes the CPU and the chipset including the IO\r
+; controllers in the chipset to enable normal operation of these devices.\r
+;\r
+;----------------------------------------------------------------------------\r
+FspSiliconInitApi PROC C PUBLIC\r
+ mov eax, 5\r
+ jmp FspApiCommon\r
+FspSiliconInitApi ENDP\r
+\r
+;----------------------------------------------------------------------------\r
+; FspApiCommon API\r
+;\r
+; This is the FSP API common entry point to resume the FSP execution\r
+;\r
+;----------------------------------------------------------------------------\r
+FspApiCommon PROC C PUBLIC\r
;\r
- ; Stack must be ready\r
+ ; EAX holds the API index\r
;\r
- push 087654321h\r
- pop eax\r
- cmp eax, 087654321h\r
+\r
+ ;\r
+ ; Stack must be ready\r
+ ; \r
+ push eax\r
+ add esp, 4\r
+ cmp eax, dword ptr [esp - 4]\r
jz @F\r
mov eax, 080000003h\r
jmp exit\r
\r
@@:\r
;\r
- ; Additional check\r
+ ; Verify the calling condition\r
;\r
pushad\r
- push 1\r
+ push [esp + 4 * 8 + 4] ; push ApiParam\r
+ push eax ; push ApiIdx\r
call FspApiCallingCheck\r
- add esp, 4\r
- mov dword ptr [esp + 4 * 7], eax\r
- popad\r
+ add esp, 8\r
cmp eax, 0\r
jz @F\r
- jmp exit\r
+ mov dword ptr [esp + 4 * 7], eax\r
+ popad\r
+ ret\r
\r
@@:\r
+ popad\r
+ cmp eax, 1 ; FspInit API\r
+ jz @F\r
+ cmp eax, 3 ; FspMemoryInit API\r
+ jz @F\r
+\r
+ call AsmGetFspInfoHeader\r
+ jmp Loader2PeiSwitchStack\r
+\r
+@@:\r
+ ;\r
+ ; FspInit and FspMemoryInit APIs, setup the initial stack frame\r
;\r
- ; Store the address in FSP which will return control to the BL\r
+ \r
;\r
- push offset exit\r
+ ; Place holder to store the FspInfoHeader pointer\r
+ ;\r
+ push eax\r
+\r
+ ;\r
+ ; Update the FspInfoHeader pointer\r
+ ;\r
+ push eax\r
+ call AsmGetFspInfoHeader\r
+ mov [esp + 4], eax\r
+ pop eax\r
\r
;\r
; Create a Task Frame in the stack for the Boot Loader\r
;\r
; Setup new FSP stack\r
;\r
- mov eax, esp\r
+ mov edi, esp\r
mov esp, PcdGet32(PcdTemporaryRamBase)\r
add esp, PcdGet32(PcdTemporaryRamSize)\r
sub esp, (DATA_LEN_AT_STACK_TOP + 40h)\r
\r
;\r
- ; Save the bootloader's stack pointer\r
+ ; Pass the API Idx to SecStartup\r
;\r
push eax\r
+ \r
+ ;\r
+ ; Pass the BootLoader stack to SecStartup\r
+ ;\r
+ push edi\r
\r
;\r
; Pass entry point of the PEI core\r
;\r
- call GetFspBaseAddress\r
- mov edi, FspImageSizeOffset\r
- mov edi, DWORD PTR [eax + edi]\r
- add edi, eax\r
+ call AsmGetFspBaseAddress\r
+ mov edi, eax\r
+ add edi, PcdGet32 (PcdFspAreaSize) \r
sub edi, 20h\r
- add eax, DWORD PTR [edi]\r
+ add eax, DWORD PTR ds:[edi]\r
push eax\r
\r
;\r
; PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs,\r
; they are different. The code below can handle both cases.\r
;\r
- call GetFspBaseAddress\r
+ call AsmGetFspBaseAddress\r
mov edi, eax\r
call GetBootFirmwareVolumeOffset\r
add eax, edi\r
; Pass Control into the PEI Core\r
;\r
call SecStartup\r
-\r
+ add esp, 4\r
exit:\r
ret\r
\r
-FspInitApi ENDP\r
-\r
-;----------------------------------------------------------------------------\r
-; NotifyPhase API\r
-;\r
-; This FSP API will notify the FSP about the different phases in the boot\r
-; process\r
-;\r
-;----------------------------------------------------------------------------\r
-NotifyPhaseApi PROC C PUBLIC\r
- ;\r
- ; Stack must be ready\r
- ;\r
- push 087654321h\r
- pop eax\r
- cmp eax, 087654321h\r
- jz @F\r
- mov eax, 080000003h\r
- jmp err_exit\r
-\r
-@@:\r
- ;\r
- ; Verify the calling condition\r
- ;\r
- pushad\r
- push 2\r
- call FspApiCallingCheck\r
- add esp, 4\r
- mov dword ptr [esp + 4 * 7], eax\r
- popad\r
-\r
- cmp eax, 0\r
- jz @F\r
-\r
- ;\r
- ; Error return\r
- ;\r
-err_exit:\r
- ret\r
-\r
-@@:\r
- jmp Pei2LoaderSwitchStack\r
-\r
-NotifyPhaseApi ENDP\r
-\r
+FspApiCommon ENDP\r
\r
END\r
projects / mirror_edk2.git / blobdiff