+++ /dev/null
-;------------------------------------------------------------------------------\r
-;\r
-; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
-; SPDX-License-Identifier: BSD-2-Clause-Patent\r
-;\r
-; Abstract:\r
-;\r
-;------------------------------------------------------------------------------\r
-\r
- .686\r
- .model flat,C\r
- .const\r
-;\r
-; Float control word initial value:\r
-; all exceptions masked, double-precision, round-to-nearest\r
-;\r
-mFpuControlWord DW 027Fh\r
-;\r
-; Multimedia-extensions control word:\r
-; all exceptions masked, round-to-nearest, flush to zero for masked underflow\r
-;\r
-mMmxControlWord DD 01F80h\r
-\r
- .xmm\r
- .code\r
-\r
-;\r
-; Initializes floating point units for requirement of UEFI specification.\r
-;\r
-; This function initializes floating-point control word to 0x027F (all exceptions\r
-; masked,double-precision, round-to-nearest) and multimedia-extensions control word\r
-; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero\r
-; for masked underflow).\r
-;\r
-InitializeFloatingPointUnits PROC PUBLIC\r
-\r
- push ebx\r
-\r
- ;\r
- ; Initialize floating point units\r
- ;\r
- finit\r
- fldcw mFpuControlWord\r
-\r
- ;\r
- ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test\r
- ; whether the processor supports SSE instruction.\r
- ;\r
- mov eax, 1\r
- cpuid\r
- bt edx, 25\r
- jnc Done\r
-\r
- ;\r
- ; Set OSFXSR bit 9 in CR4\r
- ;\r
- mov eax, cr4\r
- or eax, BIT9\r
- mov cr4, eax\r
-\r
- ;\r
- ; The processor should support SSE instruction and we can use\r
- ; ldmxcsr instruction\r
- ;\r
- ldmxcsr mMmxControlWord\r
-Done:\r
- pop ebx\r
-\r
- ret\r
-\r
-InitializeFloatingPointUnits ENDP\r
-\r
-END\r