+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
-# SPDX-License-Identifier: BSD-2-Clause-Patent\r
-#\r
-# Abstract:\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-#\r
-# Float control word initial value:\r
-# all exceptions masked, double-precision, round-to-nearest\r
-#\r
-ASM_PFX(mFpuControlWord): .word 0x027F\r
-#\r
-# Multimedia-extensions control word:\r
-# all exceptions masked, round-to-nearest, flush to zero for masked underflow\r
-#\r
-ASM_PFX(mMmxControlWord): .long 0x01F80\r
-\r
-\r
-\r
-#\r
-# Initializes floating point units for requirement of UEFI specification.\r
-#\r
-# This function initializes floating-point control word to 0x027F (all exceptions\r
-# masked,double-precision, round-to-nearest) and multimedia-extensions control word\r
-# (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero\r
-# for masked underflow).\r
-#\r
-ASM_GLOBAL ASM_PFX(InitializeFloatingPointUnits)\r
-ASM_PFX(InitializeFloatingPointUnits):\r
-\r
- pushl %ebx\r
-\r
- #\r
- # Initialize floating point units\r
- #\r
- finit\r
- fldcw ASM_PFX(mFpuControlWord)\r
-\r
- #\r
- # Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test\r
- # whether the processor supports SSE instruction.\r
- #\r
- movl $1, %eax\r
- cpuid\r
- btl $25, %edx\r
- jnc Done\r
-\r
- #\r
- # Set OSFXSR bit 9 in CR4\r
- #\r
- movl %cr4, %eax\r
- orl $BIT9, %eax\r
- movl %eax, %cr4\r
-\r
- #\r
- # The processor should support SSE instruction and we can use\r
- # ldmxcsr instruction\r
- #\r
- ldmxcsr ASM_PFX(mMmxControlWord)\r
-\r
-Done:\r
- popl %ebx\r
-\r
- ret\r