BaseTools: Library hashing fix and optimization for --hash feature

[mirror_edk2.git] / IntelFspWrapperPkg / IntelFspWrapperPkg.dec

diff --git a/IntelFspWrapperPkg/IntelFspWrapperPkg.dec b/IntelFspWrapperPkg/IntelFspWrapperPkg.dec
index bfed1cc97aec8b9c67ccbbfbbb3453ba4983a895..8b0c4338f66b8d981d227b9c2f44f44c10a16e70 100644 (file)
--- a/IntelFspWrapperPkg/IntelFspWrapperPkg.dec
+++ b/IntelFspWrapperPkg/IntelFspWrapperPkg.dec
@@ -2,13 +2,7 @@
 # Provides drivers and definitions to support fsp in EDKII bios.\r
 #\r
 # Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials are licensed and made available under\r
-# the terms and conditions of the BSD License that accompanies this distribution.\r
-# The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
 #\r
 ##\r
 \r
@@ -59,10 +53,22 @@
   ## Provides the size of the BIOS Flash Device.\r
   gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00200000|UINT32|0x10000002\r
 \r
-  ## Indicates the base address of the FSP binary.\r
+  ## Indicates the base address of the factory FSP binary.\r
   gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|0xFFF80000|UINT32|0x10000003\r
-  ## Provides the size of the FSP binary.\r
+  ## Indicates the base address of the updatable FSP binary to support Dual FSP.\r
+  #  There could be two FSP images at different locations in a flash - \r
+  #  one factory version (default) and updatable version (updatable).\r
+  #  TempRamInit, FspMemoryInit and TempRamExit are always executed from factory version.\r
+  #  FspSiliconInit and NotifyPhase can be executed from updatable version if it is available,\r
+  #  FspSiliconInit and NotifyPhase are executed from factory version if there is no updateable version,\r
+  #  PcdFlashFvFspBase is base address of factory FSP, and PcdFlashFvSecondFspBase\r
+  #  is base address of updatable FSP. If PcdFlashFvSecondFspBase is 0, that means\r
+  #  there is no updatable FSP.\r
+  gFspWrapperTokenSpaceGuid.PcdFlashFvSecondFspBase|0x00000000|UINT32|0x10000008\r
+  ## Provides the size of the factory FSP binary.\r
   gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize|0x00048000|UINT32|0x10000004\r
+  ## Provides the size of the updatable FSP binary to support Dual FSP.\r
+  gFspWrapperTokenSpaceGuid.PcdFlashFvSecondFspSize|0x00000000|UINT32|0x10000009\r
 \r
   ## Indicates the base address of the first Microcode Patch in the Microcode Region\r
   gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x10000005\r