\r
https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf\r
\r
- @note Fixed bug in the spec Mailbox3 - RM31 size from 0x45(69) to 0x46(70)\r
-\r
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
#ifndef _IGD_OPREGION_H_\r
UINT64 FDSS; ///< Offset 0x3AA DSS Buffer address allocated for IFFS feature\r
UINT32 FDSP; ///< Offset 0x3B2 Size of DSS buffer\r
UINT32 STAT; ///< Offset 0x3B6 State Indicator\r
- UINT8 RM31[0x46]; ///< Offset 0x3BA - 0x3FF Reserved Must be zero. Bug in spec 0x45(69)\r
+ UINT64 RVDA; ///< Offset 0x3BA Physical address of Raw VBT data. Added from Spec Version 0.90 to support VBT greater than 6KB.\r
+ UINT32 RVDS; ///< Offset 0x3C2 Size of Raw VBT data. Added from Spec Version 0.90 to support VBT greater than 6KB.\r
+ UINT8 RM32[0x3A]; ///< Offset 0x3C6 - 0x3FF Reserved Must be zero.\r
} IGD_OPREGION_MBOX3;\r
\r
///\r