IntelSiliconPkg: Replace BSD License with BSD+Patent License

[mirror_edk2.git] / IntelSiliconPkg / IntelSiliconPkg.dec

diff --git a/IntelSiliconPkg/IntelSiliconPkg.dec b/IntelSiliconPkg/IntelSiliconPkg.dec
index e42dbad0a75ee46582e87924ab30f8dd02c62f6e..fe5bfa0dc640212b773ee83c21c2fe4e1ece433b 100644 (file)
--- a/IntelSiliconPkg/IntelSiliconPkg.dec
+++ b/IntelSiliconPkg/IntelSiliconPkg.dec
@@ -3,14 +3,8 @@
 #\r
 # This package provides common open source Intel silicon modules.\r
 #\r
-# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials are licensed and made available under\r
-# the terms and conditions of the BSD License that accompanies this distribution.\r
-# The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
 #\r
 ##\r
 \r
@@ -22,3 +16,65 @@
 \r
 [Includes]\r
   Include\r
+\r
+[LibraryClasses.IA32, LibraryClasses.X64]\r
+  ## @libraryclass  Provides services to access Microcode region on flash device.\r
+  #\r
+  MicrocodeFlashAccessLib|Include/Library/MicrocodeFlashAccessLib.h\r
+\r
+[Guids]\r
+  ## GUID for Package token space\r
+  # {A9F8D54E-1107-4F0A-ADD0-4587E7A4A735}\r
+  gIntelSiliconPkgTokenSpaceGuid  = { 0xa9f8d54e, 0x1107, 0x4f0a, { 0xad, 0xd0, 0x45, 0x87, 0xe7, 0xa4, 0xa7, 0x35 } }\r
+\r
+  ## HOB GUID to publish SMBIOS data records from PEI phase\r
+  # HOB data format is same as SMBIOS records defined in SMBIOS spec or OEM defined types\r
+  # Generic DXE Library / Driver can locate HOB(s) and add SMBIOS records into SMBIOS table\r
+  gIntelSmbiosDataHobGuid         = { 0x798e722e, 0x15b2, 0x4e13, { 0x8a, 0xe9, 0x6b, 0xa3, 0x0f, 0xf7, 0xf1, 0x67 }}\r
+\r
+  ## Include/Guid/MicrocodeFmp.h\r
+  gMicrocodeFmpImageTypeIdGuid      = { 0x96d4fdcd, 0x1502, 0x424d, { 0x9d, 0x4c, 0x9b, 0x12, 0xd2, 0xdc, 0xae, 0x5c } }\r
+\r
+[Ppis]\r
+  gEdkiiVTdInfoPpiGuid = { 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0x67, 0xaf, 0x2b, 0x25, 0x68, 0x4a } }\r
+\r
+[Protocols]\r
+  gEdkiiPlatformVTdPolicyProtocolGuid = { 0x3d17e448, 0x466, 0x4e20, { 0x99, 0x9f, 0xb2, 0xe1, 0x34, 0x88, 0xee, 0x22 }}\r
+\r
+[PcdsFixedAtBuild, PcdsPatchableInModule]\r
+  ## Error code for VTd error.<BR><BR>\r
+  #  EDKII_ERROR_CODE_VTD_ERROR = (EFI_IO_BUS_UNSPECIFIED | (EFI_OEM_SPECIFIC | 0x00000000)) = 0x02008000<BR>\r
+  # @Prompt Error code for VTd error.\r
+  gIntelSiliconPkgTokenSpaceGuid.PcdErrorCodeVTdError|0x02008000|UINT32|0x00000005\r
+\r
+[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]\r
+  ## This is the GUID of the FFS which contains the Graphics Video BIOS Table (VBT)\r
+  # The VBT content is stored as a RAW section which is consumed by GOP PEI/UEFI driver.\r
+  # The default GUID can be updated by patching or runtime if platform support multiple VBT configurations.\r
+  # @Prompt GUID of the FFS which contains the Graphics Video BIOS Table (VBT)\r
+  # { 0x56752da9, 0xde6b, 0x4895, 0x88, 0x19, 0x19, 0x45, 0xb6, 0xb7, 0x6c, 0x22 }\r
+  gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid|{ 0xa9, 0x2d, 0x75, 0x56, 0x6b, 0xde, 0x95, 0x48, 0x88, 0x19, 0x19, 0x45, 0xb6, 0xb7, 0x6c, 0x22 }|VOID*|0x00000001\r
+\r
+  ## The mask is used to control VTd behavior.<BR><BR>\r
+  #  BIT0: Enable IOMMU during boot (If DMAR table is installed in DXE. If VTD_INFO_PPI is installed in PEI.)\r
+  #  BIT1: Enable IOMMU when transfer control to OS (ExitBootService in normal boot. EndOfPEI in S3)\r
+  #  BIT2: Force no IOMMU access attribute request recording before DMAR table is installed.\r
+  # @Prompt The policy for VTd driver behavior.\r
+  gIntelSiliconPkgTokenSpaceGuid.PcdVTdPolicyPropertyMask|1|UINT8|0x00000002\r
+\r
+  ## Declares VTd PEI DMA buffer size.<BR><BR>\r
+  #  When this PCD value is referred by platform to calculate the required\r
+  #  memory size for PEI (InstallPeiMemory), the PMR alignment requirement\r
+  #  needs be considered to be added with this PCD value for alignment\r
+  #  adjustment need by AllocateAlignedPages.\r
+  # @Prompt The VTd PEI DMA buffer size.\r
+  gIntelSiliconPkgTokenSpaceGuid.PcdVTdPeiDmaBufferSize|0x00400000|UINT32|0x00000003\r
+\r
+  ## Declares VTd PEI DMA buffer size for S3.<BR><BR>\r
+  #  When this PCD value is referred by platform to calculate the required\r
+  #  memory size for PEI S3 (InstallPeiMemory), the PMR alignment requirement\r
+  #  needs be considered to be added with this PCD value for alignment\r
+  #  adjustment need by AllocateAlignedPages.\r
+  # @Prompt The VTd PEI DMA buffer size for S3.\r
+  gIntelSiliconPkgTokenSpaceGuid.PcdVTdPeiDmaBufferSizeS3|0x00200000|UINT32|0x00000004\r
+\r