/** @file\r
The file for AHCI mode of ATA host controller.\r
\r
- Copyright (c) 2010 - 2013, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
)\r
{\r
UINT32 Value;\r
- UINT32 Delay;\r
+ UINT64 Delay;\r
+ BOOLEAN InfiniteWait;\r
\r
- Delay = (UINT32) (DivU64x32 (Timeout, 1000) + 1);\r
+ if (Timeout == 0) {\r
+ InfiniteWait = TRUE;\r
+ } else {\r
+ InfiniteWait = FALSE;\r
+ }\r
+\r
+ Delay = DivU64x32 (Timeout, 1000) + 1;\r
\r
do {\r
//\r
\r
Delay--;\r
\r
- } while (Delay > 0);\r
+ } while (InfiniteWait || (Delay > 0));\r
\r
return EFI_TIMEOUT;\r
}\r
)\r
{\r
UINT32 Value;\r
- UINT32 Delay;\r
+ UINT64 Delay;\r
+ BOOLEAN InfiniteWait;\r
+\r
+ if (Timeout == 0) {\r
+ InfiniteWait = TRUE;\r
+ } else {\r
+ InfiniteWait = FALSE;\r
+ }\r
\r
- Delay = (UINT32) (DivU64x32 (Timeout, 1000) + 1);\r
+ Delay = DivU64x32 (Timeout, 1000) + 1;\r
\r
do {\r
//\r
\r
Delay--;\r
\r
- } while (Delay > 0);\r
+ } while (InfiniteWait || (Delay > 0));\r
\r
return EFI_TIMEOUT;\r
}\r
@param[in] Address The memory address to test.\r
@param[in] MaskValue The mask value of memory.\r
@param[in] TestValue The test value of memory.\r
- @param[in, out] RetryTimes The retry times value for waitting memory set. If 0, then just try once.\r
+ @param[in, out] Task Optional. Pointer to the ATA_NONBLOCK_TASK used by\r
+ non-blocking mode. If NULL, then just try once.\r
\r
@retval EFI_NOTREADY The memory is not set.\r
@retval EFI_TIMEOUT The memory setting retry times out.\r
IN UINTN Address,\r
IN UINT32 MaskValue,\r
IN UINT32 TestValue,\r
- IN OUT UINTN *RetryTimes OPTIONAL\r
+ IN OUT ATA_NONBLOCK_TASK *Task\r
)\r
{\r
UINT32 Value;\r
\r
- if (RetryTimes != NULL) {\r
- (*RetryTimes)--;\r
+ if (Task != NULL) {\r
+ Task->RetryTimes--;\r
}\r
\r
Value = *(volatile UINT32 *) Address;\r
return EFI_SUCCESS;\r
}\r
\r
- if ((RetryTimes != NULL) && (*RetryTimes == 0)) {\r
+ if ((Task != NULL) && !Task->InfiniteWait && (Task->RetryTimes == 0)) {\r
return EFI_TIMEOUT;\r
} else {\r
return EFI_NOT_READY;\r
//\r
// Filling the PRDT\r
//\r
- PrdtNumber = (DataLength + EFI_AHCI_MAX_DATA_PER_PRDT - 1) / EFI_AHCI_MAX_DATA_PER_PRDT;\r
+ PrdtNumber = (UINT32)DivU64x32 (((UINT64)DataLength + EFI_AHCI_MAX_DATA_PER_PRDT - 1), EFI_AHCI_MAX_DATA_PER_PRDT);\r
\r
//\r
// According to AHCI 1.3 spec, a PRDT entry can point to a maximum 4MB data block.\r
VOID *Map;\r
UINTN MapLength;\r
EFI_PCI_IO_PROTOCOL_OPERATION Flag;\r
- UINT32 Delay;\r
+ UINT64 Delay;\r
EFI_AHCI_COMMAND_FIS CFis;\r
EFI_AHCI_COMMAND_LIST CmdList;\r
UINT32 PortTfd;\r
UINT32 PrdCount;\r
+ BOOLEAN InfiniteWait;\r
+\r
+ if (Timeout == 0) {\r
+ InfiniteWait = TRUE;\r
+ } else {\r
+ InfiniteWait = FALSE;\r
+ }\r
\r
if (Read) {\r
Flag = EfiPciIoOperationBusMasterWrite;\r
// Wait device sends the PIO setup fis before data transfer\r
//\r
Status = EFI_TIMEOUT;\r
- Delay = (UINT32) (DivU64x32 (Timeout, 1000) + 1);\r
+ Delay = DivU64x32 (Timeout, 1000) + 1;\r
do {\r
Offset = FisBaseAddr + EFI_AHCI_PIO_FIS_OFFSET;\r
\r
- Status = AhciCheckMemSet (Offset, EFI_AHCI_FIS_TYPE_MASK, EFI_AHCI_FIS_PIO_SETUP, 0);\r
+ Status = AhciCheckMemSet (Offset, EFI_AHCI_FIS_TYPE_MASK, EFI_AHCI_FIS_PIO_SETUP, NULL);\r
if (!EFI_ERROR (Status)) {\r
Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;\r
PortTfd = AhciReadReg (PciIo, (UINT32) Offset);\r
}\r
\r
Offset = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;\r
- Status = AhciCheckMemSet (Offset, EFI_AHCI_FIS_TYPE_MASK, EFI_AHCI_FIS_REGISTER_D2H, 0);\r
+ Status = AhciCheckMemSet (Offset, EFI_AHCI_FIS_TYPE_MASK, EFI_AHCI_FIS_REGISTER_D2H, NULL);\r
if (!EFI_ERROR (Status)) {\r
Status = EFI_DEVICE_ERROR;\r
break;\r
MicroSecondDelay(100);\r
\r
Delay--;\r
- } while (Delay > 0);\r
+ } while (InfiniteWait || (Delay > 0));\r
} else {\r
//\r
// Wait for D2H Fis is received\r
//\r
if (Task != NULL) {\r
Task->IsStart = TRUE;\r
- Task->RetryTimes = (UINT32) (DivU64x32(Timeout, 1000) + 1);\r
}\r
if (Read) {\r
Flag = EfiPciIoOperationBusMasterWrite;\r
Offset,\r
EFI_AHCI_FIS_TYPE_MASK,\r
EFI_AHCI_FIS_REGISTER_D2H,\r
- (UINTN *) (&Task->RetryTimes)\r
+ Task\r
);\r
} else {\r
Status = AhciWaitMemSet (\r
IN UINT64 Timeout\r
)\r
{\r
- UINT32 Delay;\r
+ UINT64 Delay;\r
UINT32 Value;\r
\r
AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);\r
\r
AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_RESET);\r
\r
- Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);\r
+ Delay = DivU64x32(Timeout, 1000) + 1;\r
\r
do {\r
Value = AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET);\r