UINT8\r
EFIAPI\r
IdeReadPortB (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN UINT16 Port\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN UINT16 Port\r
)\r
{\r
- UINT8 Data;\r
+ UINT8 Data;\r
\r
ASSERT (PciIo != NULL);\r
\r
PciIo,\r
EfiPciIoWidthUint8,\r
EFI_PCI_IO_PASS_THROUGH_BAR,\r
- (UINT64) Port,\r
+ (UINT64)Port,\r
1,\r
&Data\r
);\r
VOID\r
EFIAPI\r
IdeWritePortB (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN UINT16 Port,\r
- IN UINT8 Data\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN UINT16 Port,\r
+ IN UINT8 Data\r
)\r
{\r
ASSERT (PciIo != NULL);\r
PciIo,\r
EfiPciIoWidthUint8,\r
EFI_PCI_IO_PASS_THROUGH_BAR,\r
- (UINT64) Port,\r
+ (UINT64)Port,\r
1,\r
&Data\r
);\r
VOID\r
EFIAPI\r
IdeWritePortW (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN UINT16 Port,\r
- IN UINT16 Data\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN UINT16 Port,\r
+ IN UINT16 Data\r
)\r
{\r
ASSERT (PciIo != NULL);\r
PciIo,\r
EfiPciIoWidthUint16,\r
EFI_PCI_IO_PASS_THROUGH_BAR,\r
- (UINT64) Port,\r
+ (UINT64)Port,\r
1,\r
&Data\r
);\r
VOID\r
EFIAPI\r
IdeWritePortDW (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN UINT16 Port,\r
- IN UINT32 Data\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN UINT16 Port,\r
+ IN UINT32 Data\r
)\r
{\r
ASSERT (PciIo != NULL);\r
PciIo,\r
EfiPciIoWidthUint32,\r
EFI_PCI_IO_PASS_THROUGH_BAR,\r
- (UINT64) Port,\r
+ (UINT64)Port,\r
1,\r
&Data\r
);\r
VOID\r
EFIAPI\r
IdeWritePortWMultiple (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN UINT16 Port,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN UINT16 Port,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
)\r
{\r
ASSERT (PciIo != NULL);\r
PciIo,\r
EfiPciIoWidthFifoUint16,\r
EFI_PCI_IO_PASS_THROUGH_BAR,\r
- (UINT64) Port,\r
+ (UINT64)Port,\r
Count,\r
- (UINT16 *) Buffer\r
+ (UINT16 *)Buffer\r
);\r
-\r
}\r
\r
/**\r
VOID\r
EFIAPI\r
IdeReadPortWMultiple (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN UINT16 Port,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN UINT16 Port,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
)\r
{\r
ASSERT (PciIo != NULL);\r
PciIo,\r
EfiPciIoWidthFifoUint16,\r
EFI_PCI_IO_PASS_THROUGH_BAR,\r
- (UINT64) Port,\r
+ (UINT64)Port,\r
Count,\r
- (UINT16 *) Buffer\r
+ (UINT16 *)Buffer\r
);\r
-\r
}\r
\r
/**\r
VOID\r
EFIAPI\r
DumpAllIdeRegisters (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN EFI_IDE_REGISTERS *IdeRegisters,\r
- IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN EFI_IDE_REGISTERS *IdeRegisters,\r
+ IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock\r
)\r
{\r
- EFI_ATA_STATUS_BLOCK StatusBlock;\r
+ EFI_ATA_STATUS_BLOCK StatusBlock;\r
\r
ASSERT (PciIo != NULL);\r
ASSERT (IdeRegisters != NULL);\r
DEBUG ((DEBUG_ERROR, "CheckRegisterStatus()-- %02x : Error : Address Mark Not Found\n", StatusBlock.AtaError));\r
}\r
}\r
+\r
DEBUG_CODE_END ();\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
CheckStatusRegister (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN EFI_IDE_REGISTERS *IdeRegisters\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN EFI_IDE_REGISTERS *IdeRegisters\r
)\r
{\r
- UINT8 StatusRegister;\r
+ UINT8 StatusRegister;\r
\r
ASSERT (PciIo != NULL);\r
ASSERT (IdeRegisters != NULL);\r
return EFI_DEVICE_ERROR;\r
}\r
}\r
+\r
return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
DRQClear (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN EFI_IDE_REGISTERS *IdeRegisters,\r
- IN UINT64 Timeout\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN EFI_IDE_REGISTERS *IdeRegisters,\r
+ IN UINT64 Timeout\r
)\r
{\r
- UINT64 Delay;\r
- UINT8 StatusRegister;\r
- BOOLEAN InfiniteWait;\r
+ UINT64 Delay;\r
+ UINT8 StatusRegister;\r
+ BOOLEAN InfiniteWait;\r
\r
ASSERT (PciIo != NULL);\r
ASSERT (IdeRegisters != NULL);\r
InfiniteWait = FALSE;\r
}\r
\r
- Delay = DivU64x32(Timeout, 1000) + 1;\r
+ Delay = DivU64x32 (Timeout, 1000) + 1;\r
do {\r
StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);\r
\r
MicroSecondDelay (100);\r
\r
Delay--;\r
-\r
} while (InfiniteWait || (Delay > 0));\r
\r
return EFI_TIMEOUT;\r
}\r
+\r
/**\r
This function is used to poll for the DRQ bit clear in the Alternate\r
Status Register. DRQ is cleared when the device is finished\r
IN UINT64 Timeout\r
)\r
{\r
- UINT64 Delay;\r
- UINT8 AltRegister;\r
- BOOLEAN InfiniteWait;\r
+ UINT64 Delay;\r
+ UINT8 AltRegister;\r
+ BOOLEAN InfiniteWait;\r
\r
ASSERT (PciIo != NULL);\r
ASSERT (IdeRegisters != NULL);\r
InfiniteWait = FALSE;\r
}\r
\r
- Delay = DivU64x32(Timeout, 1000) + 1;\r
+ Delay = DivU64x32 (Timeout, 1000) + 1;\r
do {\r
AltRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);\r
\r
MicroSecondDelay (100);\r
\r
Delay--;\r
-\r
} while (InfiniteWait || (Delay > 0));\r
\r
return EFI_TIMEOUT;\r
IN UINT64 Timeout\r
)\r
{\r
- UINT64 Delay;\r
- UINT8 StatusRegister;\r
- UINT8 ErrorRegister;\r
- BOOLEAN InfiniteWait;\r
+ UINT64 Delay;\r
+ UINT8 StatusRegister;\r
+ UINT8 ErrorRegister;\r
+ BOOLEAN InfiniteWait;\r
\r
ASSERT (PciIo != NULL);\r
ASSERT (IdeRegisters != NULL);\r
InfiniteWait = FALSE;\r
}\r
\r
- Delay = DivU64x32(Timeout, 1000) + 1;\r
+ Delay = DivU64x32 (Timeout, 1000) + 1;\r
do {\r
//\r
// Read Status Register will clear interrupt\r
if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {\r
return EFI_ABORTED;\r
}\r
+\r
return EFI_DEVICE_ERROR;\r
}\r
\r
\r
return EFI_TIMEOUT;\r
}\r
+\r
/**\r
This function is used to poll for the DRQ bit set in the Alternate Status Register.\r
DRQ is set when the device is ready to transfer data. So this function is called after\r
IN UINT64 Timeout\r
)\r
{\r
- UINT64 Delay;\r
- UINT8 AltRegister;\r
- UINT8 ErrorRegister;\r
- BOOLEAN InfiniteWait;\r
+ UINT64 Delay;\r
+ UINT8 AltRegister;\r
+ UINT8 ErrorRegister;\r
+ BOOLEAN InfiniteWait;\r
\r
ASSERT (PciIo != NULL);\r
ASSERT (IdeRegisters != NULL);\r
InfiniteWait = FALSE;\r
}\r
\r
- Delay = DivU64x32(Timeout, 1000) + 1;\r
+ Delay = DivU64x32 (Timeout, 1000) + 1;\r
\r
do {\r
//\r
if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {\r
return EFI_ABORTED;\r
}\r
+\r
return EFI_DEVICE_ERROR;\r
}\r
\r
return EFI_TIMEOUT;\r
}\r
\r
-\r
-\r
-\r
/**\r
This function is used to poll for the BSY bit clear in the Status Register. BSY\r
is clear when the device is not busy. Every command must be sent after device is not busy.\r
IN UINT64 Timeout\r
)\r
{\r
- UINT64 Delay;\r
- UINT8 StatusRegister;\r
- BOOLEAN InfiniteWait;\r
+ UINT64 Delay;\r
+ UINT8 StatusRegister;\r
+ BOOLEAN InfiniteWait;\r
\r
ASSERT (PciIo != NULL);\r
ASSERT (IdeRegisters != NULL);\r
InfiniteWait = FALSE;\r
}\r
\r
- Delay = DivU64x32(Timeout, 1000) + 1;\r
+ Delay = DivU64x32 (Timeout, 1000) + 1;\r
do {\r
StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);\r
\r
MicroSecondDelay (100);\r
\r
Delay--;\r
-\r
} while (InfiniteWait || (Delay > 0));\r
\r
return EFI_TIMEOUT;\r
}\r
\r
-\r
/**\r
Get IDE i/o port registers' base addresses by mode.\r
\r
EFI_STATUS\r
EFIAPI\r
GetIdeRegisterIoAddr (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN OUT EFI_IDE_REGISTERS *IdeRegisters\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN OUT EFI_IDE_REGISTERS *IdeRegisters\r
)\r
{\r
- EFI_STATUS Status;\r
- PCI_TYPE00 PciData;\r
- UINT16 CommandBlockBaseAddr;\r
- UINT16 ControlBlockBaseAddr;\r
- UINT16 BusMasterBaseAddr;\r
+ EFI_STATUS Status;\r
+ PCI_TYPE00 PciData;\r
+ UINT16 CommandBlockBaseAddr;\r
+ UINT16 ControlBlockBaseAddr;\r
+ UINT16 BusMasterBaseAddr;\r
\r
if ((PciIo == NULL) || (IdeRegisters == NULL)) {\r
return EFI_INVALID_PARAMETER;\r
return Status;\r
}\r
\r
- BusMasterBaseAddr = (UINT16) ((PciData.Device.Bar[4] & 0x0000fff0));\r
+ BusMasterBaseAddr = (UINT16)((PciData.Device.Bar[4] & 0x0000fff0));\r
\r
if ((PciData.Hdr.ClassCode[0] & IDE_PRIMARY_OPERATING_MODE) == 0) {\r
CommandBlockBaseAddr = 0x1f0;\r
//\r
// The BARs should be of IO type\r
//\r
- if ((PciData.Device.Bar[0] & BIT0) == 0 ||\r
- (PciData.Device.Bar[1] & BIT0) == 0) {\r
+ if (((PciData.Device.Bar[0] & BIT0) == 0) ||\r
+ ((PciData.Device.Bar[1] & BIT0) == 0))\r
+ {\r
return EFI_UNSUPPORTED;\r
}\r
\r
- CommandBlockBaseAddr = (UINT16) (PciData.Device.Bar[0] & 0x0000fff8);\r
- ControlBlockBaseAddr = (UINT16) ((PciData.Device.Bar[1] & 0x0000fffc) + 2);\r
+ CommandBlockBaseAddr = (UINT16)(PciData.Device.Bar[0] & 0x0000fff8);\r
+ ControlBlockBaseAddr = (UINT16)((PciData.Device.Bar[1] & 0x0000fffc) + 2);\r
}\r
\r
//\r
// Calculate IDE primary channel I/O register base address.\r
//\r
IdeRegisters[EfiIdePrimary].Data = CommandBlockBaseAddr;\r
- IdeRegisters[EfiIdePrimary].ErrOrFeature = (UINT16) (CommandBlockBaseAddr + 0x01);\r
- IdeRegisters[EfiIdePrimary].SectorCount = (UINT16) (CommandBlockBaseAddr + 0x02);\r
- IdeRegisters[EfiIdePrimary].SectorNumber = (UINT16) (CommandBlockBaseAddr + 0x03);\r
- IdeRegisters[EfiIdePrimary].CylinderLsb = (UINT16) (CommandBlockBaseAddr + 0x04);\r
- IdeRegisters[EfiIdePrimary].CylinderMsb = (UINT16) (CommandBlockBaseAddr + 0x05);\r
- IdeRegisters[EfiIdePrimary].Head = (UINT16) (CommandBlockBaseAddr + 0x06);\r
- IdeRegisters[EfiIdePrimary].CmdOrStatus = (UINT16) (CommandBlockBaseAddr + 0x07);\r
+ IdeRegisters[EfiIdePrimary].ErrOrFeature = (UINT16)(CommandBlockBaseAddr + 0x01);\r
+ IdeRegisters[EfiIdePrimary].SectorCount = (UINT16)(CommandBlockBaseAddr + 0x02);\r
+ IdeRegisters[EfiIdePrimary].SectorNumber = (UINT16)(CommandBlockBaseAddr + 0x03);\r
+ IdeRegisters[EfiIdePrimary].CylinderLsb = (UINT16)(CommandBlockBaseAddr + 0x04);\r
+ IdeRegisters[EfiIdePrimary].CylinderMsb = (UINT16)(CommandBlockBaseAddr + 0x05);\r
+ IdeRegisters[EfiIdePrimary].Head = (UINT16)(CommandBlockBaseAddr + 0x06);\r
+ IdeRegisters[EfiIdePrimary].CmdOrStatus = (UINT16)(CommandBlockBaseAddr + 0x07);\r
IdeRegisters[EfiIdePrimary].AltOrDev = ControlBlockBaseAddr;\r
IdeRegisters[EfiIdePrimary].BusMasterBaseAddr = BusMasterBaseAddr;\r
\r
//\r
// The BARs should be of IO type\r
//\r
- if ((PciData.Device.Bar[2] & BIT0) == 0 ||\r
- (PciData.Device.Bar[3] & BIT0) == 0) {\r
+ if (((PciData.Device.Bar[2] & BIT0) == 0) ||\r
+ ((PciData.Device.Bar[3] & BIT0) == 0))\r
+ {\r
return EFI_UNSUPPORTED;\r
}\r
\r
- CommandBlockBaseAddr = (UINT16) (PciData.Device.Bar[2] & 0x0000fff8);\r
- ControlBlockBaseAddr = (UINT16) ((PciData.Device.Bar[3] & 0x0000fffc) + 2);\r
+ CommandBlockBaseAddr = (UINT16)(PciData.Device.Bar[2] & 0x0000fff8);\r
+ ControlBlockBaseAddr = (UINT16)((PciData.Device.Bar[3] & 0x0000fffc) + 2);\r
}\r
\r
//\r
// Calculate IDE secondary channel I/O register base address.\r
//\r
IdeRegisters[EfiIdeSecondary].Data = CommandBlockBaseAddr;\r
- IdeRegisters[EfiIdeSecondary].ErrOrFeature = (UINT16) (CommandBlockBaseAddr + 0x01);\r
- IdeRegisters[EfiIdeSecondary].SectorCount = (UINT16) (CommandBlockBaseAddr + 0x02);\r
- IdeRegisters[EfiIdeSecondary].SectorNumber = (UINT16) (CommandBlockBaseAddr + 0x03);\r
- IdeRegisters[EfiIdeSecondary].CylinderLsb = (UINT16) (CommandBlockBaseAddr + 0x04);\r
- IdeRegisters[EfiIdeSecondary].CylinderMsb = (UINT16) (CommandBlockBaseAddr + 0x05);\r
- IdeRegisters[EfiIdeSecondary].Head = (UINT16) (CommandBlockBaseAddr + 0x06);\r
- IdeRegisters[EfiIdeSecondary].CmdOrStatus = (UINT16) (CommandBlockBaseAddr + 0x07);\r
+ IdeRegisters[EfiIdeSecondary].ErrOrFeature = (UINT16)(CommandBlockBaseAddr + 0x01);\r
+ IdeRegisters[EfiIdeSecondary].SectorCount = (UINT16)(CommandBlockBaseAddr + 0x02);\r
+ IdeRegisters[EfiIdeSecondary].SectorNumber = (UINT16)(CommandBlockBaseAddr + 0x03);\r
+ IdeRegisters[EfiIdeSecondary].CylinderLsb = (UINT16)(CommandBlockBaseAddr + 0x04);\r
+ IdeRegisters[EfiIdeSecondary].CylinderMsb = (UINT16)(CommandBlockBaseAddr + 0x05);\r
+ IdeRegisters[EfiIdeSecondary].Head = (UINT16)(CommandBlockBaseAddr + 0x06);\r
+ IdeRegisters[EfiIdeSecondary].CmdOrStatus = (UINT16)(CommandBlockBaseAddr + 0x07);\r
IdeRegisters[EfiIdeSecondary].AltOrDev = ControlBlockBaseAddr;\r
- IdeRegisters[EfiIdeSecondary].BusMasterBaseAddr = (UINT16) (BusMasterBaseAddr + 0x8);\r
+ IdeRegisters[EfiIdeSecondary].BusMasterBaseAddr = (UINT16)(BusMasterBaseAddr + 0x8);\r
\r
return EFI_SUCCESS;\r
}\r
\r
-\r
/**\r
Send ATA Ext command into device with NON_DATA protocol.\r
\r
EFI_STATUS\r
EFIAPI\r
AtaIssueCommand (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN EFI_IDE_REGISTERS *IdeRegisters,\r
- IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,\r
- IN UINT64 Timeout\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN EFI_IDE_REGISTERS *IdeRegisters,\r
+ IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,\r
+ IN UINT64 Timeout\r
)\r
{\r
EFI_STATUS Status;\r
//\r
// Select device (bit4), set LBA mode(bit6) (use 0xe0 for compatibility)\r
//\r
- IdeWritePortB (PciIo, IdeRegisters->Head, (UINT8) (0xe0 | DeviceHead));\r
+ IdeWritePortB (PciIo, IdeRegisters->Head, (UINT8)(0xe0 | DeviceHead));\r
\r
//\r
// set all the command parameters\r
EFI_STATUS\r
EFIAPI\r
AtaPioDataInOut (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN EFI_IDE_REGISTERS *IdeRegisters,\r
- IN OUT VOID *Buffer,\r
- IN UINT64 ByteCount,\r
- IN BOOLEAN Read,\r
- IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,\r
- IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,\r
- IN UINT64 Timeout,\r
- IN ATA_NONBLOCK_TASK *Task\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN EFI_IDE_REGISTERS *IdeRegisters,\r
+ IN OUT VOID *Buffer,\r
+ IN UINT64 ByteCount,\r
+ IN BOOLEAN Read,\r
+ IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,\r
+ IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,\r
+ IN UINT64 Timeout,\r
+ IN ATA_NONBLOCK_TASK *Task\r
)\r
{\r
UINTN WordCount;\r
goto Exit;\r
}\r
\r
- Buffer16 = (UINT16 *) Buffer;\r
+ Buffer16 = (UINT16 *)Buffer;\r
\r
//\r
// According to PIO data in protocol, host can perform a series of reads to\r
//\r
WordCount = 0;\r
\r
- while (WordCount < RShiftU64(ByteCount, 1)) {\r
+ while (WordCount < RShiftU64 (ByteCount, 1)) {\r
//\r
// Poll DRQ bit set, data transfer can be performed only when DRQ is ready\r
//\r
//\r
// Get the byte count for one series of read\r
//\r
- if ((WordCount + Increment) > RShiftU64(ByteCount, 1)) {\r
- Increment = (UINTN)(RShiftU64(ByteCount, 1) - WordCount);\r
+ if ((WordCount + Increment) > RShiftU64 (ByteCount, 1)) {\r
+ Increment = (UINTN)(RShiftU64 (ByteCount, 1) - WordCount);\r
}\r
\r
if (Read) {\r
EFI_STATUS\r
EFIAPI\r
AtaNonDataCommandIn (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN EFI_IDE_REGISTERS *IdeRegisters,\r
- IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,\r
- IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,\r
- IN UINT64 Timeout,\r
- IN ATA_NONBLOCK_TASK *Task\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN EFI_IDE_REGISTERS *IdeRegisters,\r
+ IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,\r
+ IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,\r
+ IN UINT64 Timeout,\r
+ IN ATA_NONBLOCK_TASK *Task\r
)\r
{\r
EFI_STATUS Status;\r
**/\r
EFI_STATUS\r
AtaUdmStatusWait (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN EFI_IDE_REGISTERS *IdeRegisters,\r
- IN UINT64 Timeout\r
- )\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN EFI_IDE_REGISTERS *IdeRegisters,\r
+ IN UINT64 Timeout\r
+ )\r
{\r
- UINT8 RegisterValue;\r
- EFI_STATUS Status;\r
- UINT16 IoPortForBmis;\r
- UINT64 Delay;\r
- BOOLEAN InfiniteWait;\r
+ UINT8 RegisterValue;\r
+ EFI_STATUS Status;\r
+ UINT16 IoPortForBmis;\r
+ UINT64 Delay;\r
+ BOOLEAN InfiniteWait;\r
\r
if (Timeout == 0) {\r
InfiniteWait = TRUE;\r
break;\r
}\r
\r
- IoPortForBmis = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMIS_OFFSET);\r
+ IoPortForBmis = (UINT16)(IdeRegisters->BusMasterBaseAddr + BMIS_OFFSET);\r
RegisterValue = IdeReadPortB (PciIo, IoPortForBmis);\r
if (((RegisterValue & BMIS_ERROR) != 0) || (Timeout == 0)) {\r
DEBUG ((DEBUG_ERROR, "ATA UDMA operation fails\n"));\r
Status = EFI_SUCCESS;\r
break;\r
}\r
+\r
//\r
// Stall for 100 microseconds.\r
//\r
**/\r
EFI_STATUS\r
AtaUdmStatusCheck (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN ATA_NONBLOCK_TASK *Task,\r
- IN EFI_IDE_REGISTERS *IdeRegisters\r
- )\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN ATA_NONBLOCK_TASK *Task,\r
+ IN EFI_IDE_REGISTERS *IdeRegisters\r
+ )\r
{\r
- UINT8 RegisterValue;\r
- UINT16 IoPortForBmis;\r
- EFI_STATUS Status;\r
+ UINT8 RegisterValue;\r
+ UINT16 IoPortForBmis;\r
+ EFI_STATUS Status;\r
\r
Task->RetryTimes--;\r
\r
return EFI_DEVICE_ERROR;\r
}\r
\r
- IoPortForBmis = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMIS_OFFSET);\r
+ IoPortForBmis = (UINT16)(IdeRegisters->BusMasterBaseAddr + BMIS_OFFSET);\r
RegisterValue = IdeReadPortB (PciIo, IoPortForBmis);\r
\r
if ((RegisterValue & BMIS_ERROR) != 0) {\r
IN ATA_NONBLOCK_TASK *Task\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT16 IoPortForBmic;\r
- UINT16 IoPortForBmis;\r
- UINT16 IoPortForBmid;\r
-\r
- UINTN PrdTableSize;\r
- EFI_PHYSICAL_ADDRESS PrdTableMapAddr;\r
- VOID *PrdTableMap;\r
- EFI_PHYSICAL_ADDRESS PrdTableBaseAddr;\r
- EFI_ATA_DMA_PRD *TempPrdBaseAddr;\r
- UINTN PrdTableNum;\r
-\r
- UINT8 RegisterValue;\r
- UINTN PageCount;\r
- UINTN ByteCount;\r
- UINTN ByteRemaining;\r
- UINT8 DeviceControl;\r
-\r
- VOID *BufferMap;\r
- EFI_PHYSICAL_ADDRESS BufferMapAddress;\r
- EFI_PCI_IO_PROTOCOL_OPERATION PciIoOperation;\r
-\r
- UINT8 DeviceHead;\r
- EFI_PCI_IO_PROTOCOL *PciIo;\r
- EFI_TPL OldTpl;\r
-\r
- UINTN AlignmentMask;\r
- UINTN RealPageCount;\r
- EFI_PHYSICAL_ADDRESS BaseAddr;\r
- EFI_PHYSICAL_ADDRESS BaseMapAddr;\r
+ EFI_STATUS Status;\r
+ UINT16 IoPortForBmic;\r
+ UINT16 IoPortForBmis;\r
+ UINT16 IoPortForBmid;\r
+\r
+ UINTN PrdTableSize;\r
+ EFI_PHYSICAL_ADDRESS PrdTableMapAddr;\r
+ VOID *PrdTableMap;\r
+ EFI_PHYSICAL_ADDRESS PrdTableBaseAddr;\r
+ EFI_ATA_DMA_PRD *TempPrdBaseAddr;\r
+ UINTN PrdTableNum;\r
+\r
+ UINT8 RegisterValue;\r
+ UINTN PageCount;\r
+ UINTN ByteCount;\r
+ UINTN ByteRemaining;\r
+ UINT8 DeviceControl;\r
+\r
+ VOID *BufferMap;\r
+ EFI_PHYSICAL_ADDRESS BufferMapAddress;\r
+ EFI_PCI_IO_PROTOCOL_OPERATION PciIoOperation;\r
+\r
+ UINT8 DeviceHead;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+ EFI_TPL OldTpl;\r
+\r
+ UINTN AlignmentMask;\r
+ UINTN RealPageCount;\r
+ EFI_PHYSICAL_ADDRESS BaseAddr;\r
+ EFI_PHYSICAL_ADDRESS BaseMapAddr;\r
\r
Status = EFI_SUCCESS;\r
PrdTableMap = NULL;\r
//\r
MicroSecondDelay (1000);\r
}\r
+\r
gBS->RestoreTPL (OldTpl);\r
\r
//\r
//\r
// Set relevant IO Port address.\r
//\r
- IoPortForBmic = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMIC_OFFSET);\r
- IoPortForBmis = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMIS_OFFSET);\r
- IoPortForBmid = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMID_OFFSET);\r
+ IoPortForBmic = (UINT16)(IdeRegisters->BusMasterBaseAddr + BMIC_OFFSET);\r
+ IoPortForBmis = (UINT16)(IdeRegisters->BusMasterBaseAddr + BMIS_OFFSET);\r
+ IoPortForBmid = (UINT16)(IdeRegisters->BusMasterBaseAddr + BMID_OFFSET);\r
\r
//\r
// For Blocking mode, start the command.\r
// Calculate the number of PRD entry.\r
// Every entry in PRD table can specify a 64K memory region.\r
//\r
- PrdTableNum = (UINTN)(RShiftU64(DataLength, 16) + 1);\r
+ PrdTableNum = (UINTN)(RShiftU64 (DataLength, 16) + 1);\r
\r
//\r
// Make sure that the memory region of PRD table is not cross 64K boundary\r
//\r
ASSERT (RealPageCount > PageCount);\r
\r
- Status = PciIo->AllocateBuffer (\r
- PciIo,\r
- AllocateAnyPages,\r
- EfiBootServicesData,\r
- RealPageCount,\r
- (VOID **)&BaseAddr,\r
- 0\r
- );\r
+ Status = PciIo->AllocateBuffer (\r
+ PciIo,\r
+ AllocateAnyPages,\r
+ EfiBootServicesData,\r
+ RealPageCount,\r
+ (VOID **)&BaseAddr,\r
+ 0\r
+ );\r
if (EFI_ERROR (Status)) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
Status = PciIo->Map (\r
PciIo,\r
EfiPciIoOperationBusMasterCommonBuffer,\r
- (VOID*)(UINTN)BaseAddr,\r
+ (VOID *)(UINTN)BaseAddr,\r
&ByteCount,\r
&BaseMapAddr,\r
&PrdTableMap\r
// it means the DMA operation may be broken into several discontinuous smaller chunks.\r
// Can't handle this case.\r
//\r
- PciIo->FreeBuffer (PciIo, RealPageCount, (VOID*)(UINTN)BaseAddr);\r
+ PciIo->FreeBuffer (PciIo, RealPageCount, (VOID *)(UINTN)BaseAddr);\r
return EFI_OUT_OF_RESOURCES;\r
}\r
\r
- ZeroMem ((VOID *) ((UINTN) BaseAddr), ByteCount);\r
+ ZeroMem ((VOID *)((UINTN)BaseAddr), ByteCount);\r
\r
//\r
// Calculate the 64K align address as PRD Table base address.\r
//\r
AlignmentMask = SIZE_64KB - 1;\r
- PrdTableBaseAddr = ((UINTN) BaseAddr + AlignmentMask) & ~AlignmentMask;\r
- PrdTableMapAddr = ((UINTN) BaseMapAddr + AlignmentMask) & ~AlignmentMask;\r
+ PrdTableBaseAddr = ((UINTN)BaseAddr + AlignmentMask) & ~AlignmentMask;\r
+ PrdTableMapAddr = ((UINTN)BaseMapAddr + AlignmentMask) & ~AlignmentMask;\r
\r
//\r
// Map the host address of DataBuffer to DMA master address.\r
);\r
if (EFI_ERROR (Status) || (ByteCount != DataLength)) {\r
PciIo->Unmap (PciIo, PrdTableMap);\r
- PciIo->FreeBuffer (PciIo, RealPageCount, (VOID*)(UINTN)BaseAddr);\r
+ PciIo->FreeBuffer (PciIo, RealPageCount, (VOID *)(UINTN)BaseAddr);\r
return EFI_OUT_OF_RESOURCES;\r
}\r
\r
// Fill the PRD table with appropriate bus master address of data buffer and data length.\r
//\r
ByteRemaining = ByteCount;\r
- TempPrdBaseAddr = (EFI_ATA_DMA_PRD*)(UINTN)PrdTableBaseAddr;\r
+ TempPrdBaseAddr = (EFI_ATA_DMA_PRD *)(UINTN)PrdTableBaseAddr;\r
while (ByteRemaining != 0) {\r
if (ByteRemaining <= 0x10000) {\r
- TempPrdBaseAddr->RegionBaseAddr = (UINT32) ((UINTN) BufferMapAddress);\r
- TempPrdBaseAddr->ByteCount = (UINT16) ByteRemaining;\r
+ TempPrdBaseAddr->RegionBaseAddr = (UINT32)((UINTN)BufferMapAddress);\r
+ TempPrdBaseAddr->ByteCount = (UINT16)ByteRemaining;\r
TempPrdBaseAddr->EndOfTable = 0x8000;\r
break;\r
}\r
\r
- TempPrdBaseAddr->RegionBaseAddr = (UINT32) ((UINTN) BufferMapAddress);\r
- TempPrdBaseAddr->ByteCount = (UINT16) 0x0;\r
+ TempPrdBaseAddr->RegionBaseAddr = (UINT32)((UINTN)BufferMapAddress);\r
+ TempPrdBaseAddr->ByteCount = (UINT16)0x0;\r
\r
ByteRemaining -= 0x10000;\r
BufferMapAddress += 0x10000;\r
//\r
// Read BMIS register and clear ERROR and INTR bit\r
//\r
- RegisterValue = IdeReadPortB(PciIo, IoPortForBmis);\r
+ RegisterValue = IdeReadPortB (PciIo, IoPortForBmis);\r
RegisterValue |= (BMIS_INTERRUPT | BMIS_ERROR);\r
IdeWritePortB (PciIo, IoPortForBmis, RegisterValue);\r
\r
//\r
// Set BMIC register to identify the operation direction\r
//\r
- RegisterValue = IdeReadPortB(PciIo, IoPortForBmic);\r
+ RegisterValue = IdeReadPortB (PciIo, IoPortForBmic);\r
if (Read) {\r
RegisterValue |= BMIC_NREAD;\r
} else {\r
- RegisterValue &= ~((UINT8) BMIC_NREAD);\r
+ RegisterValue &= ~((UINT8)BMIC_NREAD);\r
}\r
+\r
IdeWritePortB (PciIo, IoPortForBmic, RegisterValue);\r
\r
if (Task != NULL) {\r
Task->Map = BufferMap;\r
Task->TableMap = PrdTableMap;\r
- Task->MapBaseAddress = (EFI_ATA_DMA_PRD*)(UINTN)BaseAddr;\r
+ Task->MapBaseAddress = (EFI_ATA_DMA_PRD *)(UINTN)BaseAddr;\r
Task->PageCount = RealPageCount;\r
Task->IsStart = TRUE;\r
}\r
Status = EFI_DEVICE_ERROR;\r
goto Exit;\r
}\r
+\r
//\r
// Set START bit of BMIC register\r
//\r
- RegisterValue = IdeReadPortB(PciIo, IoPortForBmic);\r
+ RegisterValue = IdeReadPortB (PciIo, IoPortForBmic);\r
RegisterValue |= BMIC_START;\r
- IdeWritePortB(PciIo, IoPortForBmic, RegisterValue);\r
-\r
+ IdeWritePortB (PciIo, IoPortForBmic, RegisterValue);\r
}\r
\r
//\r
// out, or a error has been happened, it needs to clear the register and free\r
// buffer.\r
//\r
- if ((Task == NULL) || Status != EFI_NOT_READY) {\r
+ if ((Task == NULL) || (Status != EFI_NOT_READY)) {\r
//\r
// Read BMIS register and clear ERROR and INTR bit\r
//\r
//\r
// Read Status Register of IDE device to clear interrupt\r
//\r
- RegisterValue = IdeReadPortB(PciIo, IdeRegisters->CmdOrStatus);\r
+ RegisterValue = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);\r
\r
//\r
// Clear START bit of BMIC register\r
//\r
- RegisterValue = IdeReadPortB(PciIo, IoPortForBmic);\r
- RegisterValue &= ~((UINT8) BMIC_START);\r
+ RegisterValue = IdeReadPortB (PciIo, IoPortForBmic);\r
+ RegisterValue &= ~((UINT8)BMIC_START);\r
IdeWritePortB (PciIo, IoPortForBmic, RegisterValue);\r
\r
//\r
// Stall for 10 milliseconds.\r
//\r
MicroSecondDelay (10000);\r
-\r
}\r
\r
Exit:\r
//\r
// Free all allocated resource\r
//\r
- if ((Task == NULL) || Status != EFI_NOT_READY) {\r
+ if ((Task == NULL) || (Status != EFI_NOT_READY)) {\r
if (Task != NULL) {\r
PciIo->Unmap (PciIo, Task->TableMap);\r
PciIo->FreeBuffer (PciIo, Task->PageCount, Task->MapBaseAddress);\r
PciIo->Unmap (PciIo, Task->Map);\r
} else {\r
PciIo->Unmap (PciIo, PrdTableMap);\r
- PciIo->FreeBuffer (PciIo, RealPageCount, (VOID*)(UINTN)BaseAddr);\r
+ PciIo->FreeBuffer (PciIo, RealPageCount, (VOID *)(UINTN)BaseAddr);\r
PciIo->Unmap (PciIo, BufferMap);\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
AtaPacketReadPendingData (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN EFI_IDE_REGISTERS *IdeRegisters\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN EFI_IDE_REGISTERS *IdeRegisters\r
)\r
{\r
- UINT8 AltRegister;\r
- UINT16 TempWordBuffer;\r
+ UINT8 AltRegister;\r
+ UINT16 TempWordBuffer;\r
\r
AltRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);\r
if ((AltRegister & ATA_STSREG_BSY) == ATA_STSREG_BSY) {\r
TempWordBuffer = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);\r
}\r
}\r
+\r
return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
AtaPacketReadWrite (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN EFI_IDE_REGISTERS *IdeRegisters,\r
- IN OUT VOID *Buffer,\r
- IN OUT UINT32 *ByteCount,\r
- IN BOOLEAN Read,\r
- IN UINT64 Timeout\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN EFI_IDE_REGISTERS *IdeRegisters,\r
+ IN OUT VOID *Buffer,\r
+ IN OUT UINT32 *ByteCount,\r
+ IN BOOLEAN Read,\r
+ IN UINT64 Timeout\r
)\r
{\r
UINT32 RequiredWordCount;\r
EFI_STATUS\r
EFIAPI\r
AtaPacketCommandExecute (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN EFI_IDE_REGISTERS *IdeRegisters,\r
- IN UINT8 Channel,\r
- IN UINT8 Device,\r
- IN EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN EFI_IDE_REGISTERS *IdeRegisters,\r
+ IN UINT8 Channel,\r
+ IN UINT8 Device,\r
+ IN EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet\r
)\r
{\r
- EFI_ATA_COMMAND_BLOCK AtaCommandBlock;\r
- EFI_STATUS Status;\r
- UINT8 Count;\r
- UINT8 PacketCommand[12];\r
+ EFI_ATA_COMMAND_BLOCK AtaCommandBlock;\r
+ EFI_STATUS Status;\r
+ UINT8 Count;\r
+ UINT8 PacketCommand[12];\r
\r
ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));\r
\r
// set the transfersize to ATAPI_MAX_BYTE_COUNT to let the device\r
// determine how many data should be transferred.\r
//\r
- AtaCommandBlock.AtaCylinderLow = (UINT8) (ATAPI_MAX_BYTE_COUNT & 0x00ff);\r
- AtaCommandBlock.AtaCylinderHigh = (UINT8) (ATAPI_MAX_BYTE_COUNT >> 8);\r
- AtaCommandBlock.AtaDeviceHead = (UINT8) (Device << 0x4);\r
+ AtaCommandBlock.AtaCylinderLow = (UINT8)(ATAPI_MAX_BYTE_COUNT & 0x00ff);\r
+ AtaCommandBlock.AtaCylinderHigh = (UINT8)(ATAPI_MAX_BYTE_COUNT >> 8);\r
+ AtaCommandBlock.AtaDeviceHead = (UINT8)(Device << 0x4);\r
AtaCommandBlock.AtaCommand = ATA_CMD_PACKET;\r
\r
IdeWritePortB (PciIo, IdeRegisters->Head, (UINT8)(0xe0 | (Device << 0x4)));\r
// Send out ATAPI command packet\r
//\r
for (Count = 0; Count < 6; Count++) {\r
- IdeWritePortW (PciIo, IdeRegisters->Data, *((UINT16*)PacketCommand + Count));\r
+ IdeWritePortW (PciIo, IdeRegisters->Data, *((UINT16 *)PacketCommand + Count));\r
//\r
// Stall for 10 microseconds.\r
//\r
return Status;\r
}\r
\r
-\r
/**\r
Set the calculated Best transfer mode to a detected device.\r
\r
IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_ATA_COMMAND_BLOCK AtaCommandBlock;\r
+ EFI_STATUS Status;\r
+ EFI_ATA_COMMAND_BLOCK AtaCommandBlock;\r
\r
ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));\r
\r
IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_ATA_COMMAND_BLOCK AtaCommandBlock;\r
+ EFI_STATUS Status;\r
+ EFI_ATA_COMMAND_BLOCK AtaCommandBlock;\r
\r
ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));\r
\r
AtaCommandBlock.AtaCommand = ATA_CMD_INIT_DRIVE_PARAM;\r
AtaCommandBlock.AtaSectorCount = DriveParameters->Sector;\r
- AtaCommandBlock.AtaDeviceHead = (UINT8) ((Device << 0x4) + DriveParameters->Heads);\r
+ AtaCommandBlock.AtaDeviceHead = (UINT8)((Device << 0x4) + DriveParameters->Heads);\r
\r
//\r
// Send Init drive parameters\r
IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_ATA_COMMAND_BLOCK AtaCommandBlock;\r
- UINT8 LBAMid;\r
- UINT8 LBAHigh;\r
+ EFI_STATUS Status;\r
+ EFI_ATA_COMMAND_BLOCK AtaCommandBlock;\r
+ UINT8 LBAMid;\r
+ UINT8 LBAHigh;\r
\r
ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));\r
\r
AtaCommandBlock.AtaFeatures = ATA_SMART_RETURN_STATUS;\r
AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;\r
AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;\r
- AtaCommandBlock.AtaDeviceHead = (UINT8) ((Device << 0x4) | 0xe0);\r
+ AtaCommandBlock.AtaDeviceHead = (UINT8)((Device << 0x4) | 0xe0);\r
\r
//\r
// Send S.M.A.R.T Read Return Status command to device\r
//\r
DEBUG ((DEBUG_INFO, "The S.M.A.R.T threshold exceeded condition is not detected\n"));\r
REPORT_STATUS_CODE (\r
- EFI_PROGRESS_CODE,\r
- (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_UNDERTHRESHOLD)\r
- );\r
+ EFI_PROGRESS_CODE,\r
+ (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_UNDERTHRESHOLD)\r
+ );\r
} else if ((LBAMid == 0xf4) && (LBAHigh == 0x2c)) {\r
//\r
// The threshold exceeded condition is detected by the device\r
//\r
DEBUG ((DEBUG_INFO, "The S.M.A.R.T threshold exceeded condition is detected\n"));\r
REPORT_STATUS_CODE (\r
- EFI_PROGRESS_CODE,\r
- (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_OVERTHRESHOLD)\r
- );\r
+ EFI_PROGRESS_CODE,\r
+ (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_OVERTHRESHOLD)\r
+ );\r
}\r
\r
return EFI_SUCCESS;\r
IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_ATA_COMMAND_BLOCK AtaCommandBlock;\r
+ EFI_STATUS Status;\r
+ EFI_ATA_COMMAND_BLOCK AtaCommandBlock;\r
\r
//\r
// Detect if the device supports S.M.A.R.T.\r
//\r
// S.M.A.R.T is not supported by the device\r
//\r
- DEBUG ((DEBUG_INFO, "S.M.A.R.T feature is not supported at [%a] channel [%a] device!\n",\r
- (Channel == 1) ? "secondary" : "primary", (Device == 1) ? "slave" : "master"));\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "S.M.A.R.T feature is not supported at [%a] channel [%a] device!\n",\r
+ (Channel == 1) ? "secondary" : "primary",\r
+ (Device == 1) ? "slave" : "master"\r
+ ));\r
REPORT_STATUS_CODE (\r
EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
(EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_NOTSUPPORTED)\r
// Check if the feature is enabled. If not, then enable S.M.A.R.T.\r
//\r
if ((IdentifyData->AtaData.command_set_feature_enb_85 & 0x0001) != 0x0001) {\r
-\r
REPORT_STATUS_CODE (\r
EFI_PROGRESS_CODE,\r
(EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_DISABLE)\r
AtaCommandBlock.AtaFeatures = ATA_SMART_ENABLE_OPERATION;\r
AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;\r
AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;\r
- AtaCommandBlock.AtaDeviceHead = (UINT8) ((Device << 0x4) | 0xe0);\r
+ AtaCommandBlock.AtaDeviceHead = (UINT8)((Device << 0x4) | 0xe0);\r
\r
//\r
// Send S.M.A.R.T Enable command to device\r
AtaCommandBlock.AtaSectorCount = 0xF1;\r
AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;\r
AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;\r
- AtaCommandBlock.AtaDeviceHead = (UINT8) ((Device << 0x4) | 0xe0);\r
+ AtaCommandBlock.AtaDeviceHead = (UINT8)((Device << 0x4) | 0xe0);\r
\r
Status = AtaNonDataCommandIn (\r
Instance->PciIo,\r
}\r
}\r
\r
- DEBUG ((DEBUG_INFO, "Enabled S.M.A.R.T feature at [%a] channel [%a] device!\n",\r
- (Channel == 1) ? "secondary" : "primary", (Device == 1) ? "slave" : "master"));\r
-\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "Enabled S.M.A.R.T feature at [%a] channel [%a] device!\n",\r
+ (Channel == 1) ? "secondary" : "primary",\r
+ (Device == 1) ? "slave" : "master"\r
+ ));\r
}\r
\r
- return ;\r
+ return;\r
}\r
\r
-\r
/**\r
Sends out an ATA Identify Command to the specified device.\r
\r
Status = AtaPioDataInOut (\r
Instance->PciIo,\r
&Instance->IdeRegisters[Channel],\r
- (VOID *) Buffer,\r
+ (VOID *)Buffer,\r
sizeof (EFI_IDENTIFY_DATA),\r
TRUE,\r
&AtaCommandBlock,\r
return Status;\r
}\r
\r
-\r
/**\r
This function is used for detect whether the IDE device exists in the\r
specified Channel as the specified Device Number.\r
IN UINT8 IdeChannel\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT8 SectorCountReg;\r
- UINT8 LBALowReg;\r
- UINT8 LBAMidReg;\r
- UINT8 LBAHighReg;\r
- EFI_ATA_DEVICE_TYPE DeviceType;\r
- UINT8 IdeDevice;\r
- EFI_IDE_REGISTERS *IdeRegisters;\r
- EFI_IDENTIFY_DATA Buffer;\r
+ EFI_STATUS Status;\r
+ UINT8 SectorCountReg;\r
+ UINT8 LBALowReg;\r
+ UINT8 LBAMidReg;\r
+ UINT8 LBAHighReg;\r
+ EFI_ATA_DEVICE_TYPE DeviceType;\r
+ UINT8 IdeDevice;\r
+ EFI_IDE_REGISTERS *IdeRegisters;\r
+ EFI_IDENTIFY_DATA Buffer;\r
\r
EFI_IDE_CONTROLLER_INIT_PROTOCOL *IdeInit;\r
EFI_PCI_IO_PROTOCOL *PciIo;\r
\r
- EFI_ATA_COLLECTIVE_MODE *SupportedModes;\r
- EFI_ATA_TRANSFER_MODE TransferMode;\r
- EFI_ATA_DRIVE_PARMS DriveParameters;\r
+ EFI_ATA_COLLECTIVE_MODE *SupportedModes;\r
+ EFI_ATA_TRANSFER_MODE TransferMode;\r
+ EFI_ATA_DRIVE_PARMS DriveParameters;\r
\r
IdeRegisters = &Instance->IdeRegisters[IdeChannel];\r
IdeInit = Instance->IdeControllerInit;\r
\r
Status = WaitForBSYClear (PciIo, IdeRegisters, 350000000);\r
if (EFI_ERROR (Status)) {\r
- DEBUG((DEBUG_ERROR, "New detecting method: Send Execute Diagnostic Command: WaitForBSYClear: Status: %d\n", Status));\r
+ DEBUG ((DEBUG_ERROR, "New detecting method: Send Execute Diagnostic Command: WaitForBSYClear: Status: %d\n", Status));\r
continue;\r
}\r
\r
continue;\r
}\r
\r
- DEBUG ((DEBUG_INFO, "[%a] channel [%a] [%a] device\n",\r
- (IdeChannel == 1) ? "secondary" : "primary ", (IdeDevice == 1) ? "slave " : "master",\r
- DeviceType == EfiIdeCdrom ? "cdrom " : "harddisk"));\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "[%a] channel [%a] [%a] device\n",\r
+ (IdeChannel == 1) ? "secondary" : "primary ",\r
+ (IdeDevice == 1) ? "slave " : "master",\r
+ DeviceType == EfiIdeCdrom ? "cdrom " : "harddisk"\r
+ ));\r
//\r
// If the device is a hard disk, then try to enable S.M.A.R.T feature\r
//\r
TransferMode.ModeCategory = EFI_ATA_MODE_FLOW_PIO;\r
}\r
\r
- TransferMode.ModeNumber = (UINT8) (SupportedModes->PioMode.Mode);\r
+ TransferMode.ModeNumber = (UINT8)(SupportedModes->PioMode.Mode);\r
\r
- if (SupportedModes->ExtModeCount == 0){\r
+ if (SupportedModes->ExtModeCount == 0) {\r
Status = SetDeviceTransferMode (Instance, IdeChannel, IdeDevice, &TransferMode, NULL);\r
\r
if (EFI_ERROR (Status)) {\r
//\r
if (SupportedModes->UdmaMode.Valid) {\r
TransferMode.ModeCategory = EFI_ATA_MODE_UDMA;\r
- TransferMode.ModeNumber = (UINT8) (SupportedModes->UdmaMode.Mode);\r
- Status = SetDeviceTransferMode (Instance, IdeChannel, IdeDevice, &TransferMode, NULL);\r
+ TransferMode.ModeNumber = (UINT8)(SupportedModes->UdmaMode.Mode);\r
+ Status = SetDeviceTransferMode (Instance, IdeChannel, IdeDevice, &TransferMode, NULL);\r
\r
if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "Set transfer Mode Fail, Status = %r\n", Status));\r
}\r
} else if (SupportedModes->MultiWordDmaMode.Valid) {\r
TransferMode.ModeCategory = EFI_ATA_MODE_MDMA;\r
- TransferMode.ModeNumber = (UINT8) SupportedModes->MultiWordDmaMode.Mode;\r
- Status = SetDeviceTransferMode (Instance, IdeChannel, IdeDevice, &TransferMode, NULL);\r
+ TransferMode.ModeNumber = (UINT8)SupportedModes->MultiWordDmaMode.Mode;\r
+ Status = SetDeviceTransferMode (Instance, IdeChannel, IdeDevice, &TransferMode, NULL);\r
\r
if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "Set transfer Mode Fail, Status = %r\n", Status));\r
//\r
// Init driver parameters\r
//\r
- DriveParameters.Sector = (UINT8) ((ATA5_IDENTIFY_DATA *)(&Buffer.AtaData))->sectors_per_track;\r
- DriveParameters.Heads = (UINT8) (((ATA5_IDENTIFY_DATA *)(&Buffer.AtaData))->heads - 1);\r
- DriveParameters.MultipleSector = (UINT8) ((ATA5_IDENTIFY_DATA *)(&Buffer.AtaData))->multi_sector_cmd_max_sct_cnt;\r
+ DriveParameters.Sector = (UINT8)((ATA5_IDENTIFY_DATA *)(&Buffer.AtaData))->sectors_per_track;\r
+ DriveParameters.Heads = (UINT8)(((ATA5_IDENTIFY_DATA *)(&Buffer.AtaData))->heads - 1);\r
+ DriveParameters.MultipleSector = (UINT8)((ATA5_IDENTIFY_DATA *)(&Buffer.AtaData))->multi_sector_cmd_max_sct_cnt;\r
\r
Status = SetDriveParameters (Instance, IdeChannel, IdeDevice, &DriveParameters, NULL);\r
}\r
REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_PC_ENABLE));\r
}\r
}\r
+\r
return EFI_SUCCESS;\r
}\r
\r
-\r
/**\r
Initialize ATA host controller at IDE mode.\r
\r
EFI_STATUS\r
EFIAPI\r
IdeModeInitialization (\r
- IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance\r
+ IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance\r
)\r
{\r
EFI_STATUS Status;\r
projects / mirror_edk2.git / blobdiff