-/** @file \r
+/** @file\r
The Ehci controller driver.\r
\r
- EhciDxe driver is responsible for managing the behavior of EHCI controller. \r
- It implements the interfaces of monitoring the status of all ports and transferring \r
+ EhciDxe driver is responsible for managing the behavior of EHCI controller.\r
+ It implements the interfaces of monitoring the status of all ports and transferring\r
Control, Bulk, Interrupt and Isochronous requests to Usb2.0 device.\r
\r
Note that EhciDxe driver is enhanced to guarantee that the EHCI controller get attached\r
- to the EHCI controller before a UHCI or OHCI driver attaches to the companion UHCI or \r
- OHCI controller. This way avoids the control transfer on a shared port between EHCI \r
- and companion host controller when UHCI or OHCI gets attached earlier than EHCI and a \r
+ to the EHCI controller before a UHCI or OHCI driver attaches to the companion UHCI or\r
+ OHCI controller. This way avoids the control transfer on a shared port between EHCI\r
+ and companion host controller when UHCI or OHCI gets attached earlier than EHCI and a\r
USB 2.0 device inserts.\r
\r
-Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution. The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
\r
*MaxSpeed = EFI_USB_SPEED_HIGH;\r
*PortNumber = (UINT8) (Ehc->HcStructParams & HCSP_NPORTS);\r
- *Is64BitCapable = (UINT8) (Ehc->HcCapParams & HCCP_64BIT);\r
+ *Is64BitCapable = (UINT8) Ehc->Support64BitDma;\r
\r
DEBUG ((EFI_D_INFO, "EhcGetCapability: %d ports, 64 bit %d\n", *PortNumber, *Is64BitCapable));\r
\r
USB2_HC_DEV *Ehc;\r
EFI_TPL OldTpl;\r
EFI_STATUS Status;\r
- UINT32 DbgCtrlStatus;\r
\r
Ehc = EHC_FROM_THIS (This);\r
\r
//\r
// Host Controller must be Halt when Reset it\r
//\r
- if (Ehc->DebugPortNum != 0) {\r
- DbgCtrlStatus = EhcReadDbgRegister(Ehc, 0);\r
- if ((DbgCtrlStatus & (USB_DEBUG_PORT_IN_USE | USB_DEBUG_PORT_OWNER)) == (USB_DEBUG_PORT_IN_USE | USB_DEBUG_PORT_OWNER)) {\r
- Status = EFI_SUCCESS;\r
- goto ON_EXIT;\r
- }\r
+ if (EhcIsDebugPortInUse (Ehc, NULL)) {\r
+ Status = EFI_SUCCESS;\r
+ goto ON_EXIT;\r
}\r
\r
if (!EhcIsHalt (Ehc)) {\r
UINTN Index;\r
UINTN MapSize;\r
EFI_STATUS Status;\r
- UINT32 DbgCtrlStatus;\r
\r
if (PortStatus == NULL) {\r
return EFI_INVALID_PARAMETER;\r
PortStatus->PortStatus = 0;\r
PortStatus->PortChangeStatus = 0;\r
\r
- if ((Ehc->DebugPortNum != 0) && (PortNumber == (Ehc->DebugPortNum - 1))) {\r
- DbgCtrlStatus = EhcReadDbgRegister(Ehc, 0);\r
- if ((DbgCtrlStatus & (USB_DEBUG_PORT_IN_USE | USB_DEBUG_PORT_OWNER)) == (USB_DEBUG_PORT_IN_USE | USB_DEBUG_PORT_OWNER)) {\r
- goto ON_EXIT;\r
- }\r
+ if (EhcIsDebugPortInUse (Ehc, &PortNumber)) {\r
+ goto ON_EXIT;\r
}\r
\r
State = EhcReadOpReg (Ehc, Offset);\r
URB *Urb;\r
EFI_TPL OldTpl;\r
EFI_STATUS Status;\r
- UINT8 *Data;\r
\r
//\r
// Validate parameters\r
\r
EhcAckAllInterrupt (Ehc);\r
\r
- Data = AllocatePool (DataLength);\r
-\r
- if (Data == NULL) {\r
- DEBUG ((EFI_D_ERROR, "EhcAsyncInterruptTransfer: failed to allocate buffer\n"));\r
-\r
- Status = EFI_OUT_OF_RESOURCES;\r
- goto ON_EXIT;\r
- }\r
-\r
- Urb = EhcCreateUrb (\r
+ Urb = EhciInsertAsyncIntTransfer (\r
Ehc,\r
DeviceAddress,\r
EndPointAddress,\r
*DataToggle,\r
MaximumPacketLength,\r
Translator,\r
- EHC_INT_TRANSFER_ASYNC,\r
- NULL,\r
- Data,\r
DataLength,\r
CallBackFunction,\r
Context,\r
);\r
\r
if (Urb == NULL) {\r
- DEBUG ((EFI_D_ERROR, "EhcAsyncInterruptTransfer: failed to create URB\n"));\r
-\r
- gBS->FreePool (Data);\r
Status = EFI_OUT_OF_RESOURCES;\r
goto ON_EXIT;\r
}\r
\r
- //\r
- // New asynchronous transfer must inserted to the head.\r
- // Check the comments in EhcMoniteAsyncRequests\r
- //\r
- EhcLinkQhToPeriod (Ehc, Urb->Qh);\r
- InsertHeadList (&Ehc->AsyncIntTransfers, &Urb->UrbList);\r
-\r
ON_EXIT:\r
Ehc->PciIo->Flush (Ehc->PciIo);\r
gBS->RestoreTPL (OldTpl);\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- if (!EHCI_IS_DATAIN (EndPointAddress)) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
if ((*DataToggle != 1) && (*DataToggle != 0)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
Status = EFI_SUCCESS;\r
}\r
\r
+ EhcFreeUrb (Ehc, Urb);\r
ON_EXIT:\r
Ehc->PciIo->Flush (Ehc->PciIo);\r
gBS->RestoreTPL (OldTpl);\r
gBS->FreePool (Ehc);\r
return NULL;\r
}\r
- \r
+\r
EhcGetUsbDebugPortInfo (Ehc);\r
\r
//\r
//\r
Status = gBS->CreateEvent (\r
EVT_TIMER | EVT_NOTIFY_SIGNAL,\r
- TPL_CALLBACK,\r
+ TPL_NOTIFY,\r
EhcMonitorAsyncRequests,\r
Ehc,\r
&Ehc->PollTimer\r
UINTN EhciBusNumber;\r
UINTN EhciDeviceNumber;\r
UINTN EhciFunctionNumber;\r
- UINT32 State;\r
EFI_DEVICE_PATH_PROTOCOL *HcDevicePath;\r
\r
//\r
goto CLOSE_PCIIO;\r
}\r
//\r
- // Determine if the device is UHCI or OHCI host controller or not. If yes, then find out the \r
+ // Determine if the device is UHCI or OHCI host controller or not. If yes, then find out the\r
// companion usb ehci host controller and force EHCI driver get attached to it before\r
// UHCI or OHCI driver attaches to UHCI or OHCI host controller.\r
//\r
if ((UsbClassCReg.ProgInterface == PCI_IF_UHCI || UsbClassCReg.ProgInterface == PCI_IF_OHCI) &&\r
- (UsbClassCReg.BaseCode == PCI_CLASS_SERIAL) && \r
+ (UsbClassCReg.BaseCode == PCI_CLASS_SERIAL) &&\r
(UsbClassCReg.SubClassCode == PCI_CLASS_SERIAL_USB)) {\r
Status = PciIo->GetLocation (\r
PciIo,\r
}\r
\r
if ((UsbClassCReg.ProgInterface == PCI_IF_EHCI) &&\r
- (UsbClassCReg.BaseCode == PCI_CLASS_SERIAL) && \r
+ (UsbClassCReg.BaseCode == PCI_CLASS_SERIAL) &&\r
(UsbClassCReg.SubClassCode == PCI_CLASS_SERIAL_USB)) {\r
Status = Instance->GetLocation (\r
Instance,\r
goto CLOSE_PCIIO;\r
}\r
\r
+ //\r
+ // Enable 64-bit DMA support in the PCI layer if this controller\r
+ // supports it.\r
+ //\r
+ if (EHC_BIT_IS_SET (Ehc->HcCapParams, HCCP_64BIT)) {\r
+ Status = PciIo->Attributes (\r
+ PciIo,\r
+ EfiPciIoAttributeOperationEnable,\r
+ EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE,\r
+ NULL\r
+ );\r
+ if (!EFI_ERROR (Status)) {\r
+ Ehc->Support64BitDma = TRUE;\r
+ } else {\r
+ DEBUG ((EFI_D_WARN,\r
+ "%a: failed to enable 64-bit DMA on 64-bit capable controller @ %p (%r)\n",\r
+ __FUNCTION__, Controller, Status));\r
+ }\r
+ }\r
+\r
Status = gBS->InstallProtocolInterface (\r
&Controller,\r
&gEfiUsb2HcProtocolGuid,\r
EhcClearLegacySupport (Ehc);\r
}\r
\r
- if (Ehc->DebugPortNum != 0) {\r
- State = EhcReadDbgRegister(Ehc, 0);\r
- if ((State & (USB_DEBUG_PORT_IN_USE | USB_DEBUG_PORT_OWNER)) != (USB_DEBUG_PORT_IN_USE | USB_DEBUG_PORT_OWNER)) {\r
- EhcResetHC (Ehc, EHC_RESET_TIMEOUT);\r
- }\r
+ if (!EhcIsDebugPortInUse (Ehc, NULL)) {\r
+ EhcResetHC (Ehc, EHC_RESET_TIMEOUT);\r
}\r
\r
Status = EhcInitHC (Ehc);\r
\r
\r
/**\r
- Stop this driver on ControllerHandle. Support stoping any child handles\r
+ Stop this driver on ControllerHandle. Support stopping any child handles\r
created by this driver.\r
\r
@param This Protocol instance pointer.\r
}\r
\r
//\r
- // Disable routing of all ports to EHCI controller, so all ports are \r
+ // Disable routing of all ports to EHCI controller, so all ports are\r
// routed back to the UHCI or OHCI controller.\r
//\r
EhcClearOpRegBit (Ehc, EHC_CONFIG_FLAG_OFFSET, CONFIGFLAG_ROUTE_EHC);\r
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