Update UHCI and ECHI drivers to both Stop and Reset the host controller at ExitBootSe...

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / EhciDxe / Ehci.h

diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h b/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h
index 006632f631e7f0a3b7f6fe23ee8fb403869c1847..f8d5444c38d3a6c86700f99fc6b28da007842fb2 100644 (file)
--- a/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h
+++ b/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h
@@ -2,8 +2,8 @@
 \r
   Provides some data struct used by EHCI controller driver.\r
 \r
-Copyright (c) 2006 - 2009, Intel Corporation\r
-All rights reserved. This program and the accompanying materials\r
+Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
 http://opensource.org/licenses/bsd-license.php\r
@@ -44,30 +44,31 @@ typedef struct _USB2_HC_DEV  USB2_HC_DEV;
 #include "EhciDebug.h"\r
 #include "ComponentName.h"\r
 \r
-typedef enum {\r
-  EHC_1_MICROSECOND            = 1,\r
-  EHC_1_MILLISECOND            = 1000 * EHC_1_MICROSECOND,\r
-  EHC_1_SECOND                 = 1000 * EHC_1_MILLISECOND,\r
+//\r
+// EHC timeout experience values\r
+//\r
 \r
-  //\r
-  // EHCI register operation timeout, set by experience\r
-  //\r
-  EHC_RESET_TIMEOUT            = 1 * EHC_1_SECOND,\r
-  EHC_GENERIC_TIMEOUT          = 10 * EHC_1_MILLISECOND,\r
+#define EHC_1_MICROSECOND            1\r
+#define EHC_1_MILLISECOND            (1000 * EHC_1_MICROSECOND)\r
+#define EHC_1_SECOND                 (1000 * EHC_1_MILLISECOND)\r
 \r
-  //\r
-  // Wait for roothub port power stable, refers to Spec[EHCI1.0-2.3.9]\r
-  //\r
-  EHC_ROOT_PORT_RECOVERY_STALL = 20 * EHC_1_MILLISECOND,\r
+//\r
+// EHCI register operation timeout, set by experience\r
+//\r
+#define EHC_RESET_TIMEOUT            (1 * EHC_1_SECOND)\r
+#define EHC_GENERIC_TIMEOUT          (10 * EHC_1_MILLISECOND)\r
 \r
-  //\r
-  // Sync and Async transfer polling interval, set by experience,\r
-  // and the unit of Async is 100us, means 50ms as interval.\r
-  //\r
-  EHC_SYNC_POLL_INTERVAL       = 1 * EHC_1_MILLISECOND,\r
-  EHC_ASYNC_POLL_INTERVAL      = 50 * 10000U\r
-} EHC_TIMEOUT_EXPERIENCE_VALUE;\r
+//\r
+// Wait for roothub port power stable, refers to Spec[EHCI1.0-2.3.9]\r
+//\r
+#define EHC_ROOT_PORT_RECOVERY_STALL (20 * EHC_1_MILLISECOND)\r
 \r
+//\r
+// Sync and Async transfer polling interval, set by experience,\r
+// and the unit of Async is 100us, means 50ms as interval.\r
+//\r
+#define EHC_SYNC_POLL_INTERVAL       (1 * EHC_1_MILLISECOND)\r
+#define EHC_ASYNC_POLL_INTERVAL      (50 * 10000U)\r
 \r
 //\r
 // EHC raises TPL to TPL_NOTIFY to serialize all its operations\r
@@ -138,8 +139,8 @@ struct _USB2_HC_DEV {
   //\r
   // Peroidic (interrupt) transfer schedule data:\r
   //\r
-  VOID                      *PeriodFrame;     // Mapped as common buffer\r
-  VOID                      *PeriodFrameHost;\r
+  VOID                      *PeriodFrame;     // the buffer pointed by this pointer is used to store pci bus address of the QH descriptor.\r
+  VOID                      *PeriodFrameHost; // the buffer pointed by this pointer is used to store host memory address of the QH descriptor.\r
   VOID                      *PeriodFrameMap;\r
 \r
   EHC_QH                    *PeriodOne;\r
@@ -151,7 +152,6 @@ struct _USB2_HC_DEV {
   UINT32                    HcStructParams; // Cache of HC structure parameter, EHC_HCSPARAMS_OFFSET\r
   UINT32                    HcCapParams;    // Cache of HC capability parameter, HCCPARAMS\r
   UINT32                    CapLen;         // Capability length\r
-  UINT32                    High32bitAddr;\r
 \r
   //\r
   // Misc\r