update Ehci driver to distinct pci memory address and host address

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / EhciDxe / EhciReg.c

diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c b/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c
index 7a533d78e13d9afd81a025985cdcee6082f78b9d..0b8187a52d73b81f01bcc5436d9bb5dacef09151 100644 (file)
--- a/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c
+++ b/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c
@@ -564,7 +564,7 @@ EhcInitHC (
   // Allocate the periodic frame and associated memeory\r
   // management facilities if not already done.\r
   //\r
-  if (Ehc->PeriodFrameHost != NULL) {\r
+  if (Ehc->PeriodFrame != NULL) {\r
     EhcFreeSched (Ehc);\r
   }\r
 \r
@@ -573,24 +573,20 @@ EhcInitHC (
   if (EFI_ERROR (Status)) {\r
     return Status;\r
   }\r
-  //\r
-  // 1. Program the CTRLDSSEGMENT register with the high 32 bit addr\r
-  //\r
-  EhcWriteOpReg (Ehc, EHC_CTRLDSSEG_OFFSET, Ehc->High32bitAddr);\r
 \r
   //\r
-  // 2. Clear USBINTR to disable all the interrupt. UEFI works by polling\r
+  // 1. Clear USBINTR to disable all the interrupt. UEFI works by polling\r
   //\r
   EhcWriteOpReg (Ehc, EHC_USBINTR_OFFSET, 0);\r
 \r
   //\r
-  // 3. Program periodic frame list, already done in EhcInitSched\r
-  // 4. Start the Host Controller\r
+  // 2. Program periodic frame list, already done in EhcInitSched\r
+  // 3. Start the Host Controller\r
   //\r
   EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);\r
 \r
   //\r
-  // 5. Set all ports routing to EHC\r
+  // 4. Set all ports routing to EHC\r
   //\r
   EhcSetOpRegBit (Ehc, EHC_CONFIG_FLAG_OFFSET, CONFIGFLAG_ROUTE_EHC);\r
 \r