--- /dev/null
+/** @file\r
+\r
+Copyright (c) 2007, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+Module Name:\r
+\r
+ EhciReg.h\r
+\r
+Abstract:\r
+\r
+ This file contains the definination for host controller register operation routines\r
+\r
+Revision History\r
+\r
+**/\r
+\r
+#ifndef _EFI_EHCI_REG_H_\r
+#define _EFI_EHCI_REG_H_\r
+\r
+\r
+enum {\r
+ //\r
+ // Capability register offset\r
+ //\r
+ EHC_CAPLENGTH_OFFSET = 0, // Capability register length offset\r
+ EHC_HCSPARAMS_OFFSET = 0x04, // Structural Parameters 04-07h\r
+ EHC_HCCPARAMS_OFFSET = 0x08, // Capability parameters offset\r
+\r
+ //\r
+ // Capability register bit definition\r
+ //\r
+ HCSP_NPORTS = 0x0F, // Number of root hub port\r
+ HCCP_64BIT = 0x01, // 64-bit addressing capability\r
+\r
+ //\r
+ // Operational register offset\r
+ //\r
+ EHC_USBCMD_OFFSET = 0x0, // USB command register offset\r
+ EHC_USBSTS_OFFSET = 0x04, // Statue register offset\r
+ EHC_USBINTR_OFFSET = 0x08, // USB interrutp offset\r
+ EHC_FRINDEX_OFFSET = 0x0C, // Frame index offset\r
+ EHC_CTRLDSSEG_OFFSET = 0x10, // Control data structure segment offset\r
+ EHC_FRAME_BASE_OFFSET = 0x14, // Frame list base address offset\r
+ EHC_ASYNC_HEAD_OFFSET = 0x18, // Next asynchronous list address offset\r
+ EHC_CONFIG_FLAG_OFFSET = 0x40, // Configure flag register offset\r
+ EHC_PORT_STAT_OFFSET = 0x44, // Port status/control offset\r
+\r
+ EHC_FRAME_LEN = 1024,\r
+\r
+ //\r
+ // Register bit definition\r
+ //\r
+ CONFIGFLAG_ROUTE_EHC = 0x01, // Route port to EHC\r
+\r
+ USBCMD_RUN = 0x01, // Run/stop\r
+ USBCMD_RESET = 0x02, // Start the host controller reset\r
+ USBCMD_ENABLE_PERIOD = 0x10, // Enable periodic schedule\r
+ USBCMD_ENABLE_ASYNC = 0x20, // Enable asynchronous schedule\r
+ USBCMD_IAAD = 0x40, // Interrupt on async advance doorbell\r
+\r
+ USBSTS_IAA = 0x20, // Interrupt on async advance\r
+ USBSTS_PERIOD_ENABLED = 0x4000, // Periodic schedule status\r
+ USBSTS_ASYNC_ENABLED = 0x8000, // Asynchronous schedule status\r
+ USBSTS_HALT = 0x1000, // Host controller halted\r
+ USBSTS_SYS_ERROR = 0x10, // Host system error\r
+ USBSTS_INTACK_MASK = 0x003F, // Mask for the interrupt ACK, the WC\r
+ // (write clean) bits in USBSTS register\r
+\r
+ PORTSC_CONN = 0x01, // Current Connect Status\r
+ PORTSC_CONN_CHANGE = 0x02, // Connect Status Change\r
+ PORTSC_ENABLED = 0x04, // Port Enable / Disable\r
+ PORTSC_ENABLE_CHANGE = 0x08, // Port Enable / Disable Change\r
+ PORTSC_OVERCUR = 0x10, // Over current Active\r
+ PORTSC_OVERCUR_CHANGE = 0x20, // Over current Change\r
+ PORSTSC_RESUME = 0x40, // Force Port Resume\r
+ PORTSC_SUSPEND = 0x80, // Port Suspend State\r
+ PORTSC_RESET = 0x100, // Port Reset\r
+ PORTSC_LINESTATE_K = 0x400, // Line Status K-state\r
+ PORTSC_LINESTATE_J = 0x800, // Line Status J-state\r
+ PORTSC_POWER = 0x1000, // Port Power\r
+ PORTSC_OWNER = 0x2000, // Port Owner\r
+ PORTSC_CHANGE_MASK = 0x2A, // Mask of the port change bits,\r
+ // they are WC (write clean)\r
+ //\r
+ // PCI Configuration Registers\r
+ //\r
+ EHC_PCI_CLASSC = 0x09,\r
+ EHC_PCI_CLASSC_PI = 0x20,\r
+ EHC_BAR_INDEX = 0, /* how many bytes away from USB_BASE to 0x10 */\r
+};\r
+\r
+#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)\r
+\r
+#define EHC_ADDR(High, QhHw32) \\r
+ ((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))\r
+\r
+#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)\r
+\r
+//\r
+// Structure to map the hardware port states to the\r
+// UEFI's port states.\r
+//\r
+typedef struct {\r
+ UINT16 HwState;\r
+ UINT16 UefiState;\r
+} USB_PORT_STATE_MAP;\r
+\r
+//\r
+// Ehci Data and Ctrl Structures\r
+//\r
+#pragma pack(1)\r
+typedef struct {\r
+ UINT8 PI;\r
+ UINT8 SubClassCode;\r
+ UINT8 BaseCode;\r
+} USB_CLASSC;\r
+#pragma pack()\r
+\r
+\r
+UINT32\r
+EhcReadCapRegister (\r
+ IN USB2_HC_DEV *Ehc,\r
+ IN UINT32 Offset\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Read EHCI capability register\r
+\r
+Arguments:\r
+\r
+ Ehc - The Ehc device\r
+ Offset - Capability register address\r
+\r
+Returns:\r
+\r
+ The register content read\r
+\r
+--*/\r
+;\r
+\r
+\r
+/**\r
+ Read Ehc Operation register\r
+\r
+ @param Ehc The EHCI device\r
+ @param Offset The operation register offset\r
+\r
+ @return The register content read\r
+\r
+**/\r
+UINT32\r
+EhcReadOpReg (\r
+ IN USB2_HC_DEV *Ehc,\r
+ IN UINT32 Offset\r
+ )\r
+;\r
+\r
+\r
+/**\r
+ Write the data to the EHCI operation register\r
+\r
+ @param Ehc The EHCI device\r
+ @param Offset EHCI operation register offset\r
+ @param Data The data to write\r
+\r
+ @return None\r
+\r
+**/\r
+VOID\r
+EhcWriteOpReg (\r
+ IN USB2_HC_DEV *Ehc,\r
+ IN UINT32 Offset,\r
+ IN UINT32 Data\r
+ )\r
+;\r
+\r
+\r
+/**\r
+ Add support for UEFI Over Legacy (UoL) feature, stop\r
+ the legacy USB SMI support\r
+\r
+ @param Ehc The EHCI device.\r
+\r
+ @return None\r
+\r
+**/\r
+VOID\r
+EhcClearLegacySupport (\r
+ IN USB2_HC_DEV *Ehc\r
+ )\r
+;\r
+\r
+\r
+\r
+/**\r
+ Set door bell and wait it to be ACKed by host controller.\r
+ This function is used to synchronize with the hardware.\r
+\r
+ @param Ehc The EHCI device\r
+ @param Timeout The time to wait before abort (in millisecond, ms)\r
+\r
+ @return EFI_SUCCESS : Synchronized with the hardware\r
+ @return EFI_TIMEOUT : Time out happened while waiting door bell to set\r
+\r
+**/\r
+EFI_STATUS\r
+EhcSetAndWaitDoorBell (\r
+ IN USB2_HC_DEV *Ehc,\r
+ IN UINT32 Timeout\r
+ )\r
+;\r
+\r
+\r
+/**\r
+ Clear all the interrutp status bits, these bits\r
+ are Write-Clean\r
+\r
+ @param Ehc The EHCI device\r
+\r
+ @return None\r
+\r
+**/\r
+VOID\r
+EhcAckAllInterrupt (\r
+ IN USB2_HC_DEV *Ehc\r
+ )\r
+;\r
+\r
+\r
+\r
+/**\r
+ Whether Ehc is halted\r
+\r
+ @param Ehc The EHCI device\r
+\r
+ @return TRUE : The controller is halted\r
+ @return FALSE : It isn't halted\r
+\r
+**/\r
+BOOLEAN\r
+EhcIsHalt (\r
+ IN USB2_HC_DEV *Ehc\r
+ )\r
+;\r
+\r
+\r
+/**\r
+ Whether system error occurred\r
+\r
+ @param Ehc The EHCI device\r
+\r
+ @return TRUE : System error happened\r
+ @return FALSE : No system error\r
+\r
+**/\r
+BOOLEAN\r
+EhcIsSysError (\r
+ IN USB2_HC_DEV *Ehc\r
+ )\r
+;\r
+\r
+\r
+\r
+/**\r
+ Reset the host controller\r
+\r
+ @param Ehc The EHCI device\r
+ @param Timeout Time to wait before abort (in millisecond, ms)\r
+\r
+ @return EFI_SUCCESS : The host controller is reset\r
+ @return Others : Failed to reset the host\r
+\r
+**/\r
+EFI_STATUS\r
+EhcResetHC (\r
+ IN USB2_HC_DEV *Ehc,\r
+ IN UINT32 Timeout\r
+ )\r
+;\r
+\r
+\r
+\r
+/**\r
+ Halt the host controller\r
+\r
+ @param Ehc The EHCI device\r
+ @param Timeout Time to wait before abort\r
+\r
+ @return EFI_SUCCESS : The EHCI is halt\r
+ @return EFI_TIMEOUT : Failed to halt the controller before Timeout\r
+\r
+**/\r
+EFI_STATUS\r
+EhcHaltHC (\r
+ IN USB2_HC_DEV *Ehc,\r
+ IN UINT32 Timeout\r
+ )\r
+;\r
+\r
+\r
+\r
+/**\r
+ Set the EHCI to run\r
+\r
+ @param Ehc The EHCI device\r
+ @param Timeout Time to wait before abort\r
+\r
+ @return EFI_SUCCESS : The EHCI is running\r
+ @return Others : Failed to set the EHCI to run\r
+\r
+**/\r
+EFI_STATUS\r
+EhcRunHC (\r
+ IN USB2_HC_DEV *Ehc,\r
+ IN UINT32 Timeout\r
+ )\r
+;\r
+\r
+\r
+\r
+/**\r
+ Initialize the HC hardware.\r
+ EHCI spec lists the five things to do to initialize the hardware\r
+ 1. Program CTRLDSSEGMENT\r
+ 2. Set USBINTR to enable interrupts\r
+ 3. Set periodic list base\r
+ 4. Set USBCMD, interrupt threshold, frame list size etc\r
+ 5. Write 1 to CONFIGFLAG to route all ports to EHCI\r
+\r
+ @param Ehc The EHCI device\r
+\r
+ @return EFI_SUCCESS : The EHCI has come out of halt state\r
+ @return EFI_TIMEOUT : Time out happened\r
+\r
+**/\r
+EFI_STATUS\r
+EhcInitHC (\r
+ IN USB2_HC_DEV *Ehc\r
+ )\r
+;\r
+\r
+#endif\r
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