MdeModulePkg/NvmExpressDxe: enable 64-bit PCI DMA

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / NvmExpressDxe / NvmExpressHci.c

diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
index dcfe1e865de569395434a4ec82ce17939b7d536e..51cff3c96c29c0e9dbd2a57940135cf5f45920a4 100644 (file)
--- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
+++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
@@ -683,6 +683,9 @@ NvmeCreateIoCompletionQueue (
   EFI_STATUS                               Status;\r
   NVME_ADMIN_CRIOCQ                        CrIoCq;\r
   UINT32                                   Index;\r
+  UINT16                                   QueueSize;\r
+\r
+  Status = EFI_SUCCESS;\r
 \r
   for (Index = 1; Index < NVME_MAX_QUEUES; Index++) {\r
     ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));\r
@@ -699,8 +702,18 @@ NvmeCreateIoCompletionQueue (
     CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;\r
     CommandPacket.QueueType      = NVME_ADMIN_QUEUE;\r
 \r
+    if (Index == 1) {\r
+      QueueSize = NVME_CCQ_SIZE;\r
+    } else {\r
+      if (Private->Cap.Mqes > NVME_ASYNC_CCQ_SIZE) {\r
+        QueueSize = NVME_ASYNC_CCQ_SIZE;\r
+      } else {\r
+        QueueSize = Private->Cap.Mqes;\r
+      }\r
+    }\r
+\r
     CrIoCq.Qid   = Index;\r
-    CrIoCq.Qsize = (Index == 1) ? NVME_CCQ_SIZE : NVME_ASYNC_CCQ_SIZE;\r
+    CrIoCq.Qsize = QueueSize;\r
     CrIoCq.Pc    = 1;\r
     CopyMem (&CommandPacket.NvmeCmd->Cdw10, &CrIoCq, sizeof (NVME_ADMIN_CRIOCQ));\r
     CommandPacket.NvmeCmd->Flags = CDW10_VALID | CDW11_VALID;\r
@@ -739,6 +752,9 @@ NvmeCreateIoSubmissionQueue (
   EFI_STATUS                               Status;\r
   NVME_ADMIN_CRIOSQ                        CrIoSq;\r
   UINT32                                   Index;\r
+  UINT16                                   QueueSize;\r
+\r
+  Status = EFI_SUCCESS;\r
 \r
   for (Index = 1; Index < NVME_MAX_QUEUES; Index++) {\r
     ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));\r
@@ -755,8 +771,18 @@ NvmeCreateIoSubmissionQueue (
     CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;\r
     CommandPacket.QueueType      = NVME_ADMIN_QUEUE;\r
 \r
+    if (Index == 1) {\r
+      QueueSize = NVME_CSQ_SIZE;\r
+    } else {\r
+      if (Private->Cap.Mqes > NVME_ASYNC_CSQ_SIZE) {\r
+        QueueSize = NVME_ASYNC_CSQ_SIZE;\r
+      } else {\r
+        QueueSize = Private->Cap.Mqes;\r
+      }\r
+    }\r
+\r
     CrIoSq.Qid   = Index;\r
-    CrIoSq.Qsize = (Index == 1) ? NVME_CSQ_SIZE : NVME_ASYNC_CSQ_SIZE;\r
+    CrIoSq.Qsize = QueueSize;\r
     CrIoSq.Pc    = 1;\r
     CrIoSq.Cqid  = Index;\r
     CrIoSq.Qprio = 0;\r
@@ -836,6 +862,19 @@ NvmeControllerInit (
     return Status;\r
   }\r
 \r
+  //\r
+  // Enable 64-bit DMA support in the PCI layer.\r
+  //\r
+  Status = PciIo->Attributes (\r
+                    PciIo,\r
+                    EfiPciIoAttributeOperationEnable,\r
+                    EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE,\r
+                    NULL\r
+                    );\r
+  if (EFI_ERROR (Status)) {\r
+    DEBUG ((EFI_D_WARN, "NvmeControllerInit: failed to enable 64-bit DMA (%r)\n", Status));\r
+  }\r
+\r
   //\r
   // Read the Controller Capabilities register and verify that the NVM command set is supported\r
   //\r