MdeModulePkg/NvmExpressDxe: Fix some bugs

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / NvmExpressDxe / NvmExpressHci.c

diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
index 157e10127aa76675ef38b981253ed5d0849f3093..7b46870d5ad33d922fbe2f2205098098a974d4d1 100644 (file)
--- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
+++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
@@ -33,21 +33,23 @@ ReadNvmeControllerCapabilities (
 {\r
   EFI_PCI_IO_PROTOCOL   *PciIo;\r
   EFI_STATUS            Status;\r
+  UINT64                Data;\r
 \r
   PciIo  = Private->PciIo;\r
   Status = PciIo->Mem.Read (\r
                         PciIo,\r
-                        EfiPciIoWidthUint64,\r
+                        EfiPciIoWidthUint32,\r
                         NVME_BAR,\r
                         NVME_CAP_OFFSET,\r
-                        1,\r
-                        Cap\r
+                        2,\r
+                        &Data\r
                         );\r
 \r
   if (EFI_ERROR(Status)) {\r
     return Status;\r
   }\r
 \r
+  WriteUnaligned64 ((UINT64*)Cap, Data);\r
   return EFI_SUCCESS;\r
 }\r
 \r
@@ -69,6 +71,7 @@ ReadNvmeControllerConfiguration (
 {\r
   EFI_PCI_IO_PROTOCOL   *PciIo;\r
   EFI_STATUS            Status;\r
+  UINT32                Data;\r
 \r
   PciIo  = Private->PciIo;\r
   Status = PciIo->Mem.Read (\r
@@ -77,13 +80,14 @@ ReadNvmeControllerConfiguration (
                         NVME_BAR,\r
                         NVME_CC_OFFSET,\r
                         1,\r
-                        Cc\r
+                        &Data\r
                         );\r
 \r
   if (EFI_ERROR(Status)) {\r
     return Status;\r
   }\r
 \r
+  WriteUnaligned32 ((UINT32*)Cc, Data);\r
   return EFI_SUCCESS;\r
 }\r
 \r
@@ -105,15 +109,17 @@ WriteNvmeControllerConfiguration (
 {\r
   EFI_PCI_IO_PROTOCOL   *PciIo;\r
   EFI_STATUS            Status;\r
+  UINT32                Data;\r
 \r
   PciIo  = Private->PciIo;\r
+  Data   = ReadUnaligned32 ((UINT32*)Cc);\r
   Status = PciIo->Mem.Write (\r
                         PciIo,\r
                         EfiPciIoWidthUint32,\r
                         NVME_BAR,\r
                         NVME_CC_OFFSET,\r
                         1,\r
-                        Cc\r
+                        &Data\r
                         );\r
 \r
   if (EFI_ERROR(Status)) {\r
@@ -149,6 +155,7 @@ ReadNvmeControllerStatus (
 {\r
   EFI_PCI_IO_PROTOCOL   *PciIo;\r
   EFI_STATUS            Status;\r
+  UINT32                Data;\r
 \r
   PciIo  = Private->PciIo;\r
   Status = PciIo->Mem.Read (\r
@@ -157,13 +164,14 @@ ReadNvmeControllerStatus (
                         NVME_BAR,\r
                         NVME_CSTS_OFFSET,\r
                         1,\r
-                        Csts\r
+                        &Data\r
                         );\r
 \r
   if (EFI_ERROR(Status)) {\r
     return Status;\r
   }\r
 \r
+  WriteUnaligned32 ((UINT32*)Csts, Data);\r
   return EFI_SUCCESS;\r
 }\r
 \r
@@ -185,6 +193,7 @@ ReadNvmeAdminQueueAttributes (
 {\r
   EFI_PCI_IO_PROTOCOL   *PciIo;\r
   EFI_STATUS            Status;\r
+  UINT32                Data;\r
 \r
   PciIo  = Private->PciIo;\r
   Status = PciIo->Mem.Read (\r
@@ -193,13 +202,14 @@ ReadNvmeAdminQueueAttributes (
                         NVME_BAR,\r
                         NVME_AQA_OFFSET,\r
                         1,\r
-                        Aqa\r
+                        &Data\r
                         );\r
 \r
   if (EFI_ERROR(Status)) {\r
     return Status;\r
   }\r
 \r
+  WriteUnaligned32 ((UINT32*)Aqa, Data);\r
   return EFI_SUCCESS;\r
 }\r
 \r
@@ -221,15 +231,17 @@ WriteNvmeAdminQueueAttributes (
 {\r
   EFI_PCI_IO_PROTOCOL   *PciIo;\r
   EFI_STATUS            Status;\r
+  UINT32                Data;\r
 \r
   PciIo  = Private->PciIo;\r
+  Data   = ReadUnaligned32 ((UINT32*)Aqa);\r
   Status = PciIo->Mem.Write (\r
                         PciIo,\r
                         EfiPciIoWidthUint32,\r
                         NVME_BAR,\r
                         NVME_AQA_OFFSET,\r
                         1,\r
-                        Aqa\r
+                        &Data\r
                         );\r
 \r
   if (EFI_ERROR(Status)) {\r
@@ -260,21 +272,23 @@ ReadNvmeAdminSubmissionQueueBaseAddress (
 {\r
   EFI_PCI_IO_PROTOCOL   *PciIo;\r
   EFI_STATUS            Status;\r
+  UINT64                Data;\r
 \r
   PciIo  = Private->PciIo;\r
   Status = PciIo->Mem.Read (\r
                         PciIo,\r
-                        EfiPciIoWidthUint64,\r
+                        EfiPciIoWidthUint32,\r
                         NVME_BAR,\r
                         NVME_ASQ_OFFSET,\r
-                        1,\r
-                        Asq\r
+                        2,\r
+                        &Data\r
                         );\r
 \r
   if (EFI_ERROR(Status)) {\r
     return Status;\r
   }\r
 \r
+  WriteUnaligned64 ((UINT64*)Asq, Data);\r
   return EFI_SUCCESS;\r
 }\r
 \r
@@ -296,15 +310,18 @@ WriteNvmeAdminSubmissionQueueBaseAddress (
 {\r
   EFI_PCI_IO_PROTOCOL   *PciIo;\r
   EFI_STATUS            Status;\r
+  UINT64                Data;\r
 \r
   PciIo  = Private->PciIo;\r
+  Data   = ReadUnaligned64 ((UINT64*)Asq);\r
+\r
   Status = PciIo->Mem.Write (\r
                         PciIo,\r
-                        EfiPciIoWidthUint64,\r
+                        EfiPciIoWidthUint32,\r
                         NVME_BAR,\r
                         NVME_ASQ_OFFSET,\r
-                        1,\r
-                        Asq\r
+                        2,\r
+                        &Data\r
                         );\r
 \r
   if (EFI_ERROR(Status)) {\r
@@ -334,21 +351,24 @@ ReadNvmeAdminCompletionQueueBaseAddress (
 {\r
   EFI_PCI_IO_PROTOCOL   *PciIo;\r
   EFI_STATUS            Status;\r
+  UINT64                Data;\r
 \r
   PciIo  = Private->PciIo;\r
+\r
   Status = PciIo->Mem.Read (\r
                         PciIo,\r
-                        EfiPciIoWidthUint64,\r
+                        EfiPciIoWidthUint32,\r
                         NVME_BAR,\r
                         NVME_ACQ_OFFSET,\r
-                        1,\r
-                        Acq\r
+                        2,\r
+                        &Data\r
                         );\r
 \r
   if (EFI_ERROR(Status)) {\r
     return Status;\r
   }\r
 \r
+  WriteUnaligned64 ((UINT64*)Acq, Data);\r
   return EFI_SUCCESS;\r
 }\r
 \r
@@ -370,15 +390,18 @@ WriteNvmeAdminCompletionQueueBaseAddress (
 {\r
   EFI_PCI_IO_PROTOCOL   *PciIo;\r
   EFI_STATUS            Status;\r
+  UINT64                Data;\r
 \r
   PciIo  = Private->PciIo;\r
+  Data   = ReadUnaligned64 ((UINT64*)Acq);\r
+\r
   Status = PciIo->Mem.Write (\r
                         PciIo,\r
-                        EfiPciIoWidthUint64,\r
+                        EfiPciIoWidthUint32,\r
                         NVME_BAR,\r
                         NVME_ACQ_OFFSET,\r
-                        1,\r
-                        Acq\r
+                        2,\r
+                        &Data\r
                         );\r
 \r
   if (EFI_ERROR(Status)) {\r
@@ -921,6 +944,25 @@ NvmeControllerInit (
     Private->ControllerData = NULL;\r
     return EFI_NOT_FOUND;\r
   }\r
+\r
+  //\r
+  // Dump NvmExpress Identify Controller Data\r
+  //\r
+  Private->ControllerData->Sn[19] = 0;\r
+  Private->ControllerData->Mn[39] = 0;\r
+  DEBUG ((EFI_D_INFO, " == NVME IDENTIFY CONTROLLER DATA ==\n"));\r
+  DEBUG ((EFI_D_INFO, "    PCI VID   : 0x%x\n", Private->ControllerData->Vid));\r
+  DEBUG ((EFI_D_INFO, "    PCI SSVID : 0x%x\n", Private->ControllerData->Ssvid));\r
+  DEBUG ((EFI_D_INFO, "    SN        : %a\n",   (CHAR8 *)(Private->ControllerData->Sn)));\r
+  DEBUG ((EFI_D_INFO, "    MN        : %a\n",   (CHAR8 *)(Private->ControllerData->Mn)));\r
+  DEBUG ((EFI_D_INFO, "    FR        : 0x%x\n", *((UINT64*)Private->ControllerData->Fr)));\r
+  DEBUG ((EFI_D_INFO, "    RAB       : 0x%x\n", Private->ControllerData->Rab));\r
+  DEBUG ((EFI_D_INFO, "    IEEE      : 0x%x\n", *(UINT32*)Private->ControllerData->Ieee_oiu));\r
+  DEBUG ((EFI_D_INFO, "    AERL      : 0x%x\n", Private->ControllerData->Aerl));\r
+  DEBUG ((EFI_D_INFO, "    SQES      : 0x%x\n", Private->ControllerData->Sqes));\r
+  DEBUG ((EFI_D_INFO, "    CQES      : 0x%x\n", Private->ControllerData->Cqes));\r
+  DEBUG ((EFI_D_INFO, "    NN        : 0x%x\n", Private->ControllerData->Nn));\r
+\r
   return Status;\r
 }\r
 \r