1) Add type cast for better coding style.

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / NvmExpressDxe / NvmExpressHci.c

diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
index 62eb39a7d6efdd0b0c3106d728108a2133b05de9..ac09fc2bd82f70ef51ee97b11f7d8e65656471b9 100644 (file)
--- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
+++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
@@ -2,7 +2,7 @@
   NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows\r
   NVM Express specification.\r
 \r
-  Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -430,6 +430,8 @@ NvmeDisableController (
   NVME_CC                Cc;\r
   NVME_CSTS              Csts;\r
   EFI_STATUS             Status;\r
+  UINT32                 Index;\r
+  UINT8                  Timeout;\r
 \r
   //\r
   // Read Controller Configuration Register.\r
@@ -450,19 +452,35 @@ NvmeDisableController (
     return Status;\r
   }\r
 \r
-  gBS->Stall(10000);\r
-\r
   //\r
-  // Check if the controller is reset\r
+  // Cap.To specifies max delay time in 500ms increments for Csts.Rdy to transition from 1 to 0 after\r
+  // Cc.Enable transition from 1 to 0. Loop produces a 1 millisecond delay per itteration, up to 500 * Cap.To.\r
   //\r
-  Status = ReadNvmeControllerStatus (Private, &Csts);\r
+  if (Private->Cap.To == 0) {\r
+    Timeout = 1;\r
+  } else {\r
+    Timeout = Private->Cap.To;\r
+  }\r
 \r
-  if (EFI_ERROR(Status)) {\r
-    return Status;\r
+  for(Index = (Timeout * 500); Index != 0; --Index) {\r
+    gBS->Stall(1000);\r
+\r
+    //\r
+    // Check if the controller is initialized\r
+    //\r
+    Status = ReadNvmeControllerStatus (Private, &Csts);\r
+\r
+    if (EFI_ERROR(Status)) {\r
+      return Status;\r
+    }\r
+\r
+    if (Csts.Rdy == 0) {\r
+      break;\r
+    }\r
   }\r
 \r
-  if (Csts.Rdy != 0) {\r
-    return EFI_DEVICE_ERROR;\r
+  if (Index == 0) {\r
+    Status = EFI_DEVICE_ERROR;\r
   }\r
 \r
   DEBUG ((EFI_D_INFO, "NVMe controller is disabled with status [%r].\n", Status));\r
@@ -798,7 +816,7 @@ NvmeControllerInit (
                     );\r
 \r
   if (!EFI_ERROR (Status)) {\r
-    Supports &= EFI_PCI_DEVICE_ENABLE;\r
+    Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;\r
     Status    = PciIo->Attributes (\r
                          PciIo,\r
                          EfiPciIoAttributeOperationEnable,\r
@@ -959,7 +977,7 @@ NvmeControllerInit (
   DEBUG ((EFI_D_INFO, "    MN        : %a\n",   (CHAR8 *)(Private->ControllerData->Mn)));\r
   DEBUG ((EFI_D_INFO, "    FR        : 0x%x\n", *((UINT64*)Private->ControllerData->Fr)));\r
   DEBUG ((EFI_D_INFO, "    RAB       : 0x%x\n", Private->ControllerData->Rab));\r
-  DEBUG ((EFI_D_INFO, "    IEEE      : 0x%x\n", *(UINT32*)Private->ControllerData->Ieee_oiu));\r
+  DEBUG ((EFI_D_INFO, "    IEEE      : 0x%x\n", *(UINT32*)Private->ControllerData->Ieee_oui));\r
   DEBUG ((EFI_D_INFO, "    AERL      : 0x%x\n", Private->ControllerData->Aerl));\r
   DEBUG ((EFI_D_INFO, "    SQES      : 0x%x\n", Private->ControllerData->Sqes));\r
   DEBUG ((EFI_D_INFO, "    CQES      : 0x%x\n", Private->ControllerData->Cqes));\r